Are you and academic and thinking of buying a Xilinx development kit?

Then I can't plug Digilent enough. They have two very large FPGA boards available for very keen prices. The first is the Xilinx XUP, which is a XC2VP30 Virtex 2 Pro with 2 405PPC cores. This board supports DDR and is a great way to get started with prototyping Gaisler SoC designs. The excellent academic price is only $299! One word of warning: this board doesn't have true SATA ports depite there being connectors and labels saying SATA. They are high speed digital data links that are SATA like but are SATA non-standard and cannot connect to a SATA HDD. No out of band signals.

The second is an uprated ML505. This is identical to the standard Xilinx ML505, but it has a much larger FPGA on it (XC5VLX110T) and comes with a JTAG programmer. The ML505 from Xilinx doesn't. Total price $750.

I have hunted about and the prices here end up hundreds of pounds less than full commercial prices. In the case of the ML505 it is about £300.

Update to AHB Slave Shenanigans and Massive Modelsim Migranes

AHB Slave Shenanigans: The HREADY signal is supposed to be an input from all the other AHB slaves such that they all can note that a slave is hanging the master.

Massive Modelsim Migranes: After a lot of messing about I found out the following solution (for 64 bit linux on amd64 and intel amd64 ext systems):

libhm = $MODEL_TECH/../linux_x86_64/libhm.sl

instead of the libhm.sl line in step 4 of this article from Xilinx. This applies to Modelsim SE 6.3f and the Rocket IO (or Rocket I/O?) module called MGT internally and the SmartModel SWIFT models included in Xilinx ISE9.2i.

I'm getting a Virtex-5 ML505

Which, to me is great news. Up till now I have been using the excellent Xilinx XUP board however it has one real failing: the ports labelled SATA on the XUP are not capable of talking to SATA devices. They don't support Out Of Band signalling.

The Virtex-5 LXT based ML505 however does support the full SATA specification, as well as a lot of others besides. The reason is more advanced Rocket IO ports.

Trouble! Things that were working just fine, now are not

Basically the system now claims it cannot see the DDR! Which is a blow. I don't know why but I am getting the dreaded 'stack pointer not set' errors and the system doesn't seem to think it has any memory. I am wondering if I need to add in a bit more manual deskewing or whether I have actually broken something (I certainly hope not!).

More to follow....

Snapgear Linux or Angstrom..

I am currently building and deploying Snapgear linux onto a LEON3 system aboard a xilinx-xup board. However I have several issues with Snapgear:

1. Despite all the hard work that has gone into it, it feels poorly constructed. I think they are discovering just how hard it is to maintain and build embedded linux distros. I am thinking of the early days of OpenZaurus
   
2. Functionality that just doesn't work out of the box: dhclient, openssl, ssh and sshd. Pretty fundamental tools here. Not to complain about the good work of uCdot

I think I shall try to get Ångström up and running as it is much better at handling these things. The main effort will be:

1. Toolchain. Assembling the patches and CFLAGS etc for the toolchain (glibc in the first instance).
2. Backend: Packaging the system such that it will be able to build images for the various GR tools.

Further posts will follow as I address these issues. Overall I think it is more valuable than fixing problems in Snapgear.

A brand new XUP board is sitting on my desk...

... and even better it doesn't have the old jtag programmer onboard so it works with GRMON! So much better than the serial debug system I was using before. It programs about 10 times faster for a start.

MSc Projects offered...

I have offered the following MSc projects:

1. Remove the LEON3 core and substitute an OpenSPARC (possibly the single core, wishbone compatible variant).
2. Build a SATA controller
3. Explore the LEON3 GRLIB design space on ASIC and FPGA (i.e. how fast, how big, etc)
4. Build an AHB parallel port (high speed, of course. Maybe a bit of a ram buffer?)
5. Enable the Xilinx-XUP board's CF card to program the FPGA, install a boot loader and boot linux.

They are all different vairants of tricky, with 5 probably a real problem in disguise. I think it would be best for the boot loader to be part of the FPGA (i.e. a 1k ROM or similar) to boot off the CF card.

Linux successfully executed!

Here is the first console dump of my executing linux session (the image.dsu was borrowed from the theora project). I shall have to consider that a success. Now onto the stickier proposition of how to boot and execute from a flash card using the xilinx-xup board. I am thinking of using systemACE to package the kernel and bitfile, and then targetting a linux partition on the CF card. It all depends if system ACE can actually put things into RAM, but I believe it can look like FLASH to the FPGA so all should be alright.

M:\GRMON\win32>grmon-eval.exe -uart //./com8 -ibaud 250000 -u -nb

GRMON LEON debug monitor v1.1.29 (evaluation version)

Copyright (C) 2004,2005 Gaisler Research - all rights reserved.
For latest updates, go to http://www.gaisler.com/
Comments or bug-reports to support@gaisler.com

This evaluation version will expire on 15/10/2008
try open device //./com8
###opened device //./com8

GRLIB build version: 2950

initialising ..............
detected frequency: 80 MHz

Component Vendor
LEON3 SPARC V8 Processor Gaisler Research
AHB Debug UART Gaisler Research
AHB Debug JTAG TAP Gaisler Research
GR Ethernet MAC Gaisler Research
AHB ROM Gaisler Research
AHB/APB Bridge Gaisler Research
LEON3 Debug Support Unit Gaisler Research
DDR266 Controller Gaisler Research
Generic APB UART Gaisler Research
Multi-processor Interrupt Ctrl Gaisler Research
Modular Timer Unit Gaisler Research
Keyboard PS/2 interface Gaisler Research
Text-based VGA controller Gaisler Research
Keyboard PS/2 interface Gaisler Research

Use command 'info sys' to print a detailed report of attached cores

grlib> load M:\Downloads\image.dsu
section: .stage2 at 0x40000000, size 10180 bytes
section: .vmlinux at 0x40004000, size 1232960 bytes
section: .rdimage at 0x40148f94, size 1598828 bytes
total size: 2841968 bytes (88.3 kbit/s)
read 3706 symbols
entry point: 0x40000000
grlib> run
Booting Linux
Booting Linux...
PROMLIB: Sun Boot Prom Version 0 Revision 0
Linux version 2.6.21.1 (root@brazilip-tec) (gcc version 3.2.2) #16 Mon Aug 20 19
:32:42 BRT 2007
ARCH: LEON
Vendors Slaves
Ahb masters:
0( 1: 3| 0): VENDOR_GAISLER GAISLER_LEON3
1( 1: 7| 0): VENDOR_GAISLER GAISLER_AHBUART
2( 1: 1c| 0): VENDOR_GAISLER GAISLER_AHBJTAG
3( 1: 1d| 0): VENDOR_GAISLER GAISLER_ETHMAC
Ahb slaves:
0( 1: 1b| 0): VENDOR_GAISLER Unknown device 1b
+0: 0x0 (raw:0x3fff2)
1( 1: 6| 0): VENDOR_GAISLER GAISLER_APBMST
+0: 0x80000000 (raw:0x8000fff2)
2( 1: 4| 0): VENDOR_GAISLER GAISLER_LEON3DSU
+0: 0x90000000 (raw:0x9000f002)
3( 1: 25| 0): VENDOR_GAISLER Unknown device 25
+0: 0x40000000 (raw:0x4003c002)
+1: 0xfff00100 (raw:0x10fff3)
Apb slaves:
0( 1: c| 2): VENDOR_GAISLER GAISLER_APBUART
+ 0: 0x80000100 (raw:0x10fff1)
1( 1: d| 0): VENDOR_GAISLER GAISLER_IRQMP
+ 0: 0x80000200 (raw:0x20fff1)
2( 1: 11| 8): VENDOR_GAISLER GAISLER_GPTIMER
+ 0: 0x80000300 (raw:0x30fff1)
3( 1: 7| 0): VENDOR_GAISLER GAISLER_AHBUART
+ 0: 0x80000400 (raw:0x40fff1)
4( 1: 60| 5): VENDOR_GAISLER GAISLER_KBD
+ 0: 0x80000500 (raw:0x50fff1)
5( 1: 61| 0): VENDOR_GAISLER GAISLER_VGA
+ 0: 0x80000600 (raw:0x60fff1)
6( 1: 60| 4): VENDOR_GAISLER GAISLER_KBD
+ 0: 0x80000700 (raw:0x70fff1)
7( 1: 1d|12): VENDOR_GAISLER GAISLER_ETHMAC
+ 0: 0x80000b00 (raw:0xb0fff1)
TYPE: Leon2/3 System-on-a-Chip
Ethernet address: 0:0:0:0:0:0
CACHE: direct mapped cache, set size 8k
Boot time fixup v1.6. 4/Mar/98 Jakub Jelinek (jj@ultra.linux.cz). Patching kerne
l for srmmu[Leon2]/iommu
64MB HIGHMEM available.
node 2: /cpu00 (type:cpu) (props:.node device_type mid mmu-nctx clock-frequency
uart1_baud uart2_baud )
PROM: Built device tree from rootnode 1 with 918 bytes of memory.
DEBUG: psr.impl = 0xf fsr.vers = 0x7
Built 1 zonelists. Total pages: 64302
Kernel command line: console=ttyS0,38400 init=/sbin/init
PID hash table entries: 1024 (order: 10, 4096 bytes)
Todo: init master_l10_counter
Attaching grlib apbuart serial drivers (clk:80hz):
Console: colour dummy device 80x25
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
Memory: 252736k/262144k available (968k kernel code, 9244k reserved, 112k data,
116k init, 65536k highmem)
Mount-cache hash table entries: 512
checking if image is initramfs...it isn't (no cpio magic); looks like an initrd
Freeing initrd memory: 1561k freed
highmem bounce pool size: 64 pages
io scheduler noop registered
io scheduler cfq registered (default)
grlib apbuart: 1 serial driver(s) at [0x80000100(irq 2)]
grlib apbuart: system frequency: 80000 khz, baud rates: 38400 38400
ttyS0 at MMIO 0x80000100 (irq = 2) is a Leon
Loading theora ...
LEON THEORA driver by Andre Costa (2007) - andre.lnc@gmail.com
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
loop: loaded (max 8 devices)
RAMDISK: Compressed image found at block 0
VFS: Mounted root (romfs filesystem) readonly.
Freeing unused kernel memory: 116k freed
init started: BusyBox v0.60.5 (2007.08.04-05:15+0000) multi-call binary
Shell invoked to run file: /etc/init.d/rcS
Command: #!/bin/sh
Command: mount
Please press Enter to activate this console.
Interrupt!
stopped at 0xf00140d0
grlib>

Just connected to my first LEON3 SoC

... via the JTAG debugger but I am still unable to drive the DDR due to the lack of DCM modules in this particular Xilinx. I am now turning my attention to the XUP board from Digilent as they are quite common around here.

Hopefully I shall get further down that road towards the goal of booting linux on the system....

Trouble with the ML403...

Heh, should have realised it wouldn't be that easy...

Basically the ML403 differs from the ML401 & 2 by the fact that they both their Virtex-4's have 8 DCMs as opposed the 403's 4, and the LEON3 core with a DDR controller (necessary for the built in DDR memory) needs 5. It took a surprisingly long time for me to realise that's what the error message meant. Still today has been quite productive with a lot of lessons learnt.

Another lesson is that Xilinx ISE on windows will rebuild a Xilinx ISE on linux project, meaning the 20 minutes I took building and routing the first design came to nothing, as the windows machine proceeded to take about 60 minutes to perform the same task.