Workshop Presentation from DAC2015: A Holistic Platform for Education in ASIC Design & Manufacturing

I was fortunate enough to be invited by Cadence to present at a Workshop 9: Interdisciplinary Academia Industry Collaboration Models and Partnerships at DAC 2015 in San Francisco.

Here is the presentation I gave, "A Holistic Platform for Education in ASIC Design & Manufacturing" on our current work with undergraduates on SoCs.

MSc Projects offered...

I have offered the following MSc projects:

1. Remove the LEON3 core and substitute an OpenSPARC (possibly the single core, wishbone compatible variant).
2. Build a SATA controller
3. Explore the LEON3 GRLIB design space on ASIC and FPGA (i.e. how fast, how big, etc)
4. Build an AHB parallel port (high speed, of course. Maybe a bit of a ram buffer?)
5. Enable the Xilinx-XUP board's CF card to program the FPGA, install a boot loader and boot linux.

They are all different vairants of tricky, with 5 probably a real problem in disguise. I think it would be best for the boot loader to be part of the FPGA (i.e. a 1k ROM or similar) to boot off the CF card.