The LEON3 sparc linux bootloader generation process is awful

1. Uses a combination of make and perl scripts reading from a global config.
2. Includes including includes including includes.
   
3. Variables drawn directly from .config files and the aforementioned headers, some of which are written by perl scripts driven from variables as above.
   
4. Uses gcc to edit a text file and then calls the result a .o (it is plain ASCII) after hardcoding all of the paths.

I either choose to sanitise this system, or just package it and gingerly push options in its general direction. It is also unclear what license it is under, however as it is part of a linux distro build process I believe that puts it under the GPL whether it is explicit or not.

MSc Projects offered...

I have offered the following MSc projects:

1. Remove the LEON3 core and substitute an OpenSPARC (possibly the single core, wishbone compatible variant).
2. Build a SATA controller
3. Explore the LEON3 GRLIB design space on ASIC and FPGA (i.e. how fast, how big, etc)
4. Build an AHB parallel port (high speed, of course. Maybe a bit of a ram buffer?)
5. Enable the Xilinx-XUP board's CF card to program the FPGA, install a boot loader and boot linux.

They are all different vairants of tricky, with 5 probably a real problem in disguise. I think it would be best for the boot loader to be part of the FPGA (i.e. a 1k ROM or similar) to boot off the CF card.

Just connected to my first LEON3 SoC

... via the JTAG debugger but I am still unable to drive the DDR due to the lack of DCM modules in this particular Xilinx. I am now turning my attention to the XUP board from Digilent as they are quite common around here.

Hopefully I shall get further down that road towards the goal of booting linux on the system....