Converting Libraries for use in Cadence PKS

Our designkits (which shall remain unspecified except that you can get some of them from CMP) mainly support Synopsys tools. However we have limited licenses for Design Compiler so to use them in Cadence PKS you can use a nifty little program called syn2tlf. This converts .lib files to .tlf, used by Cadence PKS. What I don't yet know is how to check that the conversion is anywhere near sane.

STmicroelectronic 65nm, 65nm SOI and 45nm Design Kit NDA's Signed

Never underestimate the time it takes to sign a legal commitment! Finally I found the right person who was able to sign for the University binding us to not revealing secrets and accepting liabilities such that I can now receive the STMicroelectronic Design Kits (Cadence calls them PDK's) from CMP for their 65nm, 65nm SOI and 45nm CMOS processes.

Now to develop several flows including various verification strategies and frontends (Synopsys' Designware, Cadence IC, PrimeTime, etc).