Current activity with the EVE ZeBu Hardware/Software Co-Verification Environment

The title is a fancy way of referring to the EVE ZeBu accelerators (much more information on their website). I previously posted on our acquisition of a UF-2 (I should mention we liked it so much we now have 2!) so I am taking a moment to show what we are up to with this wonderful technology. I have broken it into research and teaching topics.

Research
Behavioural Simulation and Synthesis of Biological Neuron Systems using VHDL
The investigation of neuron structures is an incredibly difficult and complex task that yields relatively low rewards in terms of information from biological forms (either animals or tissue). The structures and connectivity of even the simplest invertebrates are almost impossible to establish with standard laboratory techniques, and even when this is possible it is generally time consuming, complex and expensive. Recent work has shown how a simplified behavioural approach to modelling neurons can allow “virtual” experiments to be carried out that map the behaviour of a simulated structure onto a hypothetical biological one, with correlation of behaviour rather than underlying connectivity. The problems with such approaches are numerous. The first is the difficulty of simulating realistic aggregates efficiently, the second is making sense of the results and finally, it would be helpful to have an implementation that could be synthesised to hardware for acceleration. In this paper we present a VHDL implementation of Neuron models that allow large aggregates to be simulated. The models are demonstrated using a synthesizable system level VHDL model of the C. Elegans locomotory system.
The role of the EVE in this specific project is verifying and executing the largest of the neural net models functionality using your cosimulation replacing previous, limited, technology based around a FPGA board using a probe program.
Publications
Bailey, J., Wilson, P., Brown, A. and Chad, J. (2008) Behavioural Simulation and Synthesis of Biological Neuron Systems using VHDL. In: BMAS. (In Press)
Bailey, J., Wilson, P. R., Brown, A. D. and Chad, J. (2007) Behavioural Simulation of Biological Neuron Systems using VHDL and VHDL-AMS. In: IEEE Behavioural Modeling and Simulation, Sep 2007, San Jose, USA. pp. 153-158.

Architectures for Numerical Computation

Since the 1960s, the observation that has become known as Moore’s Law has become a self-fulfilling prophecy. Processing power doubles every two years because of the advances in CMOS technology. There are clear signs, however, that these technological advances are coming to an end. The eco- nomics of pushing CMOS technology to its physical limits will eventually halt further development.
If it is no longer feasible to increase computing power through smaller, faster transistors, the al- ternative is massive parallelism. This progression is already apparent. Multi-core and multi-threaded processors are now common. Although modern operating systems are able to use multiple cores, with few exceptions, programs are confined to single cores. The challenge facing software engineers is to make best use of multiple cores.
A significant amount of processing power is concerned with numerical computation. Consumer applications, such as image and audio processing are fundamentally numerical. Similarly, engineering applications, such as simulation and optimization rely on numerical calculations. At this point, we should distinguish between consumer and desktop applications and High-Performance Computing (HPC) tasks that rely on clusters of dedicated processors. It is not our intention to move into the HPC world at this time.
While using multiple cores can accelerate many numerical algorithms, far greater speed-up would be possible using more specialized forms of hardware, such as GPUs and FPGAs. A further consideration is power consumption (and the related problem of heat dissipation). Custom hardware can reduce power consumption by an order of magnitude or more. The key, of course, is to use the resources in the best possible way. In the context of the work proposed here, there are two aspects to this problem. First, we need to make the best division between hardware and software and second, we need to design an appropriate overall architecture.
The obvious role of the EVE platform in this research field is to support the research into specific computing pipelines, fine grain computation blocks and architectures as well as enabling the development of some 16 lane PCIe computation accelerators.

Teaching
Hosting a Complex SoC on the EVE Platform
This project was a proof of concept and de-risking of the EVE transactor flow using a large SoC. The SoC in question was chosen to be the Gaisler-Aeroflex LEON3 (http://www.gaisler.com). The LEON3 SoC is based around a SPARC v8 compatible CPU and is written in VHDL. The minimal LEON3 SoC was built using the EVE support for memory to model the processor cache along with the transactors for DRAM and UARTs. This work will be extended to include the VGA, Ethernet and USB transactors on the hardware side it and include support for the Snapgear Linux version for the LEON3.

Verification of a highly integrated ASIC
A large masters level project framework will produce a heterogeneous multicore ASIC to perform processing on HD video data streams. It will bundle an 32 bit microcontroller core, on chip SRAM, our custom geometric processor along with a multilayer AMBA bus architecture optimised for power and contention. The EVE will be an invaluable support to the simulation and verification of the final design before it is sent for manufacture.

So there you have it - quite a lot going on, all of which is really fascinating and fun!

Modding an HP Proliant DL585 to take an EVE Zebu UF2

I am the proud "controller" of an EVE Zebu UF2 emulation accelerator (a big PCI card covered in FPGAs). One of its biggest selling points is their Transactors which allow you to present your design with the interfaces it would experience if it were real, completely abstracting away the PCI bus.

However when I say big I mean triple height and full length. It uses 64 bit PCI/66. (For those considering purchasing a UF4 card most PCs can't fit it as it is larger still).

So I need a computer to host it in!

Enter the HP DL585 - a lovely machine. Built as solidly as a tank and everything is terribly easily accessible either from the front or the top. Everything. At a push I think I could swap out the motherboard and be back up and running in 30 minutes from cracking the case.

The original engineers designed it for cable-less operation (and very nearly succeeded!) but the EVE ZeBu-UF needs power from a 4 pin molex (found on most pre-SATA HDDs).

So what to do? Spotting this SCA backplane and knowing that HDDs take 12V, 5V and 3.3V power I had my solution. Mod a molex connector onto the pins on the back of one of the SCA sockets.

Firstly I checked the specifications for the ZeBu: 25W at 12V which is a current of 2.08A. Secondly I checked the specifications of the SCA2 connector: Section 6.4.1 of the SFF-8046 standard specifies a surge current of 5A and a constant supply of 2.5A. This means that one socket can supply the necessary power.

However, several provisos first: This will void your warranty. The SCA-2 connector transfers power to the drive using several pins for each voltage (12V, 5V and 3.3V) to reduce their resistivity to high current. By design the clusters of pins supplying the same voltage are next to each other making it easier. Probe for the resistance between the pins you think are the right ones - it needs to be zero.

The mod requires soldering the little clusters of pins together with fine wire (get some strands out of a multistrand wire) and then attached the cables. Note - don't include the Precharge pins - wiring them to the rest of the supply could cause unexpected operation as they will no longer function correctly when you insert a HDD in the front. After you are done, check, double check and triple check. Use a magnifier/microscope to check the soldering. Clean the area of any bits of solder. Probe the resistivity again. This could be an expensive mistake if there is a problem!

Power on (fingers crossed) and bingo - 12V and 5V.

Here is a photo of the modded card in position:


...and a photo of the UF2 in the PCI bay (I have two power connectors just in case I can get another UF2 - wishful thinking I know):

MSc Dissertation Titles for 2009

1. An OpenSPARC with Hypertransport
Add a memory mapped Hypertransport port to an OpenSPARC processor.

2. SystemC to Reality
Take the Synopsys innovator SystemC based example of an MP3 player and
convert as much as possible to real hardware to assess the accuracy of
the Virtual Platform Model using the EVE accelerator.

3. Accelerating Geometric Mathematics
Taking the departments Geometric Maths co processor design and attaching
it to an IBM PowerPC 405 processor (either memory mapped or via the
coprocessor port) as efficiently as possible.

4. Hardening Soft Cores, the advantages and problems
Take the LEON3 opensource Sparc v8 processor and the IBM PowerPC 405
processor softcores (one is VHDL, one Verilog) and study them for speed
and size optimisations using blocks inside an FPGA like embedded
ram/multipliers. The LEON3 is already optimised and will serve as an
example.

5. Bi-width Processing for Sensor Applications
Research and design a processor with 2 data word widths - 8bits for low
power mode and an additional 32 bits when turned into high power mode.

Research the LEAP architecture first and try to improve it.