Just P&R'ed and unconstrained SoC using Cadence Encounter

Excellent, a LEON3, DDR controller, misc peripherals using a ST Microelectronics 120nm process from CMP. It was badly done, unconstrained and in all likelihood completely non-functional but it is a real start.
Taking it forward:

1. Verifying the rc generated verilog netlist is functionally correct. Modelsim will work for us here.
2. Using rc to generate the netlist from two technology files: Low Leakage and High Speed to allow the critical path to run faster.
   
3. Generalizing the setup of Encounter such that it fully uses the whole designkit in an easy-to-use package.
   
4. P&R'ing a whole SoC.
5. Verifying the back-extracted layout is fully correct.