Taking it forward:
- Verifying the rc generated verilog netlist is functionally correct. Modelsim will work for us here.
- Using rc to generate the netlist from two technology files: Low Leakage and High Speed to allow the critical path to run faster.
- Generalizing the setup of Encounter such that it fully uses the whole designkit in an easy-to-use package.
- P&R'ing a whole SoC.
- Verifying the back-extracted layout is fully correct.