I have just used Cadence SoC's rc (RTL Compiler) to build a verilog netlist of a LEON3 SoC. The estimates are that it would run at 300MHz on a 120nm process.
Now I just need to progress getting it into encounter to start floorplanning. And a large amount of verification and checking that it is valid and correct.
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Hi,
ReplyDeleteI am Brazilian Master Student at UFRGS. I tried to synthetize the LEON 3 Processor using RTL Compiler(Cadence), but i did not obtain success.
Would I like knowledge if you have some tip about to synthetize the LEON 3 using RTL Compiler ?
Thanks,
Daniel Guimarães Jr.