Tuesday, 2 September 2008

Cadence rc LEON3 compilation success

I have just used Cadence SoC's rc (RTL Compiler) to build a verilog netlist of a LEON3 SoC. The estimates are that it would run at 300MHz on a 120nm process.

Now I just need to progress getting it into encounter to start floorplanning. And a large amount of verification and checking that it is valid and correct.

1 comment:

  1. Hi,
    I am Brazilian Master Student at UFRGS. I tried to synthetize the LEON 3 Processor using RTL Compiler(Cadence), but i did not obtain success.
    Would I like knowledge if you have some tip about to synthetize the LEON 3 using RTL Compiler ?

    Thanks,
    Daniel GuimarĂ£es Jr.

    ReplyDelete