Friday, 25 September 2009

"Transmute" - Design Philosopies

I realized that I had forgotten to describe a very, very important step: Philosophy. In this case I am using the word incorrectly. It is actually World View that I mean. From Wikipedia:
"A comprehensive world view (or worldview) is the fundamental cognitive orientation of an individual or society encompassing natural philosophy, fundamental existential and normative postulates or themes, values, emotions, and ethics."
Now what has this to do with chip design? Well you might ask! In this case it is the fundamental underpinnings and assumptions that surround the design.

The world view is formed from facts and opinions and our emotional reaction to them.

So here is the list of suitable facts for the "Transmute" project:
  • We have only built cell based custom digital cores
  • None of our typical projects are as large as this
  • The design flows are not stable - considerable development will be required
  • Several custom digital modules will be required to interfaced to licensed IP
  • We can experiment with power saving strategies
  • We are very experienced with custom analogue blocks
What, as a designer, is my emotional reaction to this? Simply this: Excitement and Concern. There are a lot of unknowns.

Hence our design World View (although a different design will have a different world view):

  • Digitally Conservative
  • Analogue Progressive
One you articulate this World View clearly you realize that this is the guide for your choices, in our case:
  • Hard IP: Eliminates the risk from core synthesis
  • Digital part to be separable from the analogue part so we can drive them separately. This will minimize the cost in case of failure or error - we would get at least one working part from the chip
  • Digital power saving strategies to be applied only after a high confidence in non-power saving digital structures obtained
  • It must be possible to disable the digital power saving structures if they are added
  • Flow decisions should favour tools which we have experience with
These decisions then guide the rest of the design flow. Also new choices can be matched against the worldview ensuring consistency.

Just bear in mind, your world view for this design may need modifying as the project progresses however if it does then you need to reconsider most of the work you have already carried out. This is typically far more important if your original plan was aggressive and you move to conservative - check work and assumptions already made!

Wednesday, 16 September 2009

The next SoC design - working title "Transmute" begins

I have a fun new hobby - designing the digital part of a new, mixed signal SoC which we are building here. It is my intention to blog the full design flow discussing the various challenges and issues as we encounter them.

Design Basics
  • Foundry
  • Technology
  • IP
  • Flow
The importance of these choices of these depends on the following thoughts:
  • What have we done before
  • Who have we worked with before
  • What have we got that works
  • What we need to do and what we would like to do
Planning a chip begins after you decide the basics above, i.e. foundry, technology and the needed parts and finally tool support. Sometimes in industry you have the luxury of a couple of other choices e.g.:
  • Cell library (we use the ST supplied one but there are others, Faraday for example)
Basic Overview Spec
  1. Two full custom ADCs for testing and evaluation
  2. A single core SoC to test our mixed signal integration and apply tests
  3. Simple connectivity to the SoC
Initial Decisions

In our case after some mulling over our experiences we decided on:
  1. ST Microelectronics via the Circuits Multi-Projets MPW broker
  2. Their HCMOS9 130nm process
  3. IP Blocks (see below)
  4. The flow, more on that later
 IP Blocks

As a university our access to IP is somewhat limited. Making a SoC requires quite a few modules like memory controllers etc.

However to the rescue rides Synopsys' DesignWare Library. It includes a basic selection of AMBA AHB/APB bus connected peripheral set and a memory controller which supports SDRAM and Flash.

To drive the the DesignWare library is the coreTools GUI (which is surprisingly hard to find) which in a nice graphical environment enables you to construct AMBA bus structures containing DesignWare peripherals. So this drives our choice of some of the tools (coreTools and DesignCompiler Ultra) as well as their DesignWare basic IP.

Onto a much more interesting question. What core to use? Considering our other IP is AMBA an ARM is the most likely choice however there are others we might use:
  • The LEON3 from Aeroflex is a Opensource (GPL), VHDL 32 bit SPARCv8 CPU with an AMBA bus. It is, however, very much bound to its peripheral library and autoconfiguration so would take a lot of work. It would also need to be customised to use the HCMOS9 SRAM blocks
  • The IBM PPC 405 is a 32 bit PowerPC core designed for embedding which is licensed to universities for teaching and education. It is the distribution created for the Synopsys flow which allows easy integration with AMBA peripherals. It is a softcore, i.e. it would need to be synthesised from RTL
In this case we wish to reduce our risk and design effort. Licensable from CMP is a foundry guaranteed ARM946E-S hard IP (i.e. they have already synthesized it and checked it) on their 130nm process. So we are going ahead with DesignWare soft IP surrounding a hard IP ARM946E-S. The benefits of hard IP are that ST have de-risked the design for us.

The features of the ARM946E-S are:
  • Excellent compiler/OS/application support. ARM is one of the best supported architectures in both Opensource and commercial software
  • Small and quick, approximately 3mm2 and clocking at 200MHz (both of these are significantly derated estimates at this stage of the design
  • MMU allowing full OS support
In addition we need the following types of IP:
  • A PLL - this is pretty much required for any SoC these days (available from CMP)
  • Level shifters and isolators - needed to try advanced power saving strategies in digital logic
The current initial design of the digital segment of our chip is best shown in a block diagram below:




We will talk of flows and the analogue integration later.....

Thursday, 3 September 2009

The sheer size of an old Sun "midrange" server

This one is going back a bit but I have obtained it for legacy support. Its a Sun V880 with 6x UltraSPARC III 750MHz processors and 12GB of RAM. Still a computer to be reckoned with [Update: Spent $50 on a new CPU/RAM board to take it to 8x CPU and 16GB RAM. eBay is great for this kind of thing]



Its as high as my desk, as large as a fridge lying on its side and sounds like a very loud aircon. [Update: When it is running under an OS at low load it throttles the fans and becomes quite quiet]

This one was going to be built with Solaris 10 on a software mirrored root using UFS but the new spin of Solaris 10 allows installation and booting off ZFS. A much more sensible choice when I have 6x 36GB disks.