Friday, 6 November 2009

IBM PowerPC™ 405-S: Getting started

Synthesizable RTL versions of IBM's excellent embeddable PowerPC™ line of processors (the 405, 460 and the 460 FPU) are available to SoC designers from Synopsys' Star IP Program and this Star IP PowerPC™ 405-S is also available to Educators. Further embeddable PowerPC™ cores for synthesis are also available from AMCC.

In a series of articles I will show how to take the educational soft IP download, verify the 405 core and put it to work bonded to some of Synopsys' DesignWare IP.

Currently the articles in this series are:

1) Getting started with the synthesizable IBM PowerPC405™ (this article)
2) Verification of the RTL with the supplied Artisan PDK (now owned by ARM)
3) Synthesis of the RTL with the supplied Artisan PDK
4) Verification of the Gate Level Netlist


It was with great excitement that I received the educational IP by electronic transfer. As is typical with this kind of IP the full details remain secret until the licenses are signed, but with the kind permission of IBM and Synopsys let me lift the veil a little bit for you:

Here is what you get:
  1. Synopsys PowerPC™ 405-S Design View CoreKit v1.00a - This enables full, accurate simulations to be carried out to allow evaluation of the core running a software stack
  2. Synopsys PowerPC™ 405-S Implementation View CoreKit v1.00a - This bundle contains the verilog RTL of the actual core itself along with a demonstration technology library and the verification tools to enable its functionality to be fully exercised and guaranteed. This view also contains implementation scripts to build the design from RTL through synthesis, DFT, floorplanning, placement and clock tree expansion.
  3. Specifications - An essential set of manuals describing the exact operation of the core
  4. DDR2 Memory Controller - IBM's PLB DDR2 SDRAM memory controller to allow attachment of off chip SDRAM
  5. SRAM Memory Controller - This allows a number of internal SRAM (not SDRAM!) blocks to be presented as one continuous memory space on the PLB bus to a master
  6. PCIX Controller - IBM's PLB to PCIX controller
  7. PLB Crossbar Arbiter - This enables the connection of a large number of PLB masters to one or more slave busses. With this block very complex multicore/multimaster bus structures can be created within an SoC
  8. DMA Controller - a standard component allowing DMA transfers between peripherals and memory and vice versa
  9. UIC Controller - This is the Universal Interrupt Controller, an essential device for any SoC 
  10. PLB to AHB Bridge - This is bundled in with the core but is well worth noting - this allows the use of DesignWare IP blocks which are based around the AMBA bus specification
  11. Artisan PDK - For simulation purposes an Artisan 130nm LV PDK is supplied
  12. IBM RISCWatch - A JTAG debugger to allow full trace and debugging functions on the PowerPC core
As you can see it is an embarrassment of riches - a near complete set of IP enabling a basic single core to a complex multicore PowerPC™ 405 based SoC to be realized with only the basic IO IPs outstanding (e.g. no serial port or GPIO).

Again I should like to say a heartfelt thankyou to IBM and Synopsys for making this IP available to Universities to drive our research and educational programs forward. It is also available to drive commercial embedded designs forward after licensing.

Note: As it is a Synopsys Star IP this distribution is designed for a number of industry standard simulators and the Synopsys Implementation and Signoff tool suite. The package contains pure Verilog RTL so it is technically possible to use another vendor's synthesis tool but that is well outside the scope of this series of articles (as well as being a very big job).

Published with permission from IBM and Synopsys

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