1. An OpenSPARC with Hypertransport
Add a memory mapped Hypertransport port to an OpenSPARC processor.
2. SystemC to Reality
Take the Synopsys innovator SystemC based example of an MP3 player and
convert as much as possible to real hardware to assess the accuracy of
the Virtual Platform Model using the EVE accelerator.
3. Accelerating Geometric Mathematics
Taking the departments Geometric Maths co processor design and attaching
it to an IBM PowerPC 405 processor (either memory mapped or via the
coprocessor port) as efficiently as possible.
4. Hardening Soft Cores, the advantages and problems
Take the LEON3 opensource Sparc v8 processor and the IBM PowerPC 405
processor softcores (one is VHDL, one Verilog) and study them for speed
and size optimisations using blocks inside an FPGA like embedded
ram/multipliers. The LEON3 is already optimised and will serve as an
5. Bi-width Processing for Sensor Applications
Research and design a processor with 2 data word widths - 8bits for low
power mode and an additional 32 bits when turned into high power mode.
Research the LEAP architecture first and try to improve it.