Monday, 30 June 2008

A brand new XUP board is sitting on my desk...

... and even better it doesn't have the old jtag programmer onboard so it works with GRMON! So much better than the serial debug system I was using before. It programs about 10 times faster for a start.

Where to go from here: System C + Hardware/Software Codesign?

The GRLIB components and tools by being GPL'ed and available in VHDL form are a serious attraction for Hardware/Software Codesign.

It isn't quite clear yet how usable/possible this will be, but it would allow us access to real, selectable hardware examples. Quite a proposition.

Friday, 27 June 2008

MSc Projects offered...

I have offered the following MSc projects:

  1. Remove the LEON3 core and substitute an OpenSPARC (possibly the single core, wishbone compatible variant).
  2. Build a SATA controller
  3. Explore the LEON3 GRLIB design space on ASIC and FPGA (i.e. how fast, how big, etc)
  4. Build an AHB parallel port (high speed, of course. Maybe a bit of a ram buffer?)
  5. Enable the Xilinx-XUP board's CF card to program the FPGA, install a boot loader and boot linux.
They are all different vairants of tricky, with 5 probably a real problem in disguise. I think it would be best for the boot loader to be part of the FPGA (i.e. a 1k ROM or similar) to boot off the CF card.

Thursday, 26 June 2008

Linux successfully executed!

Here is the first console dump of my executing linux session (the image.dsu was borrowed from the theora project). I shall have to consider that a success. Now onto the stickier proposition of how to boot and execute from a flash card using the xilinx-xup board. I am thinking of using systemACE to package the kernel and bitfile, and then targetting a linux partition on the CF card. It all depends if system ACE can actually put things into RAM, but I believe it can look like FLASH to the FPGA so all should be alright.

M:\GRMON\win32>grmon-eval.exe -uart //./com8 -ibaud 250000 -u -nb

GRMON LEON debug monitor v1.1.29 (evaluation version)

Copyright (C) 2004,2005 Gaisler Research - all rights reserved.
For latest updates, go to
Comments or bug-reports to

This evaluation version will expire on 15/10/2008
try open device //./com8
###opened device //./com8

GRLIB build version: 2950

initialising ..............
detected frequency: 80 MHz

Component Vendor
LEON3 SPARC V8 Processor Gaisler Research
AHB Debug UART Gaisler Research
AHB Debug JTAG TAP Gaisler Research
GR Ethernet MAC Gaisler Research
AHB ROM Gaisler Research
AHB/APB Bridge Gaisler Research
LEON3 Debug Support Unit Gaisler Research
DDR266 Controller Gaisler Research
Generic APB UART Gaisler Research
Multi-processor Interrupt Ctrl Gaisler Research
Modular Timer Unit Gaisler Research
Keyboard PS/2 interface Gaisler Research
Text-based VGA controller Gaisler Research
Keyboard PS/2 interface Gaisler Research

Use command 'info sys' to print a detailed report of attached cores

grlib> load M:\Downloads\image.dsu
section: .stage2 at 0x40000000, size 10180 bytes
section: .vmlinux at 0x40004000, size 1232960 bytes
section: .rdimage at 0x40148f94, size 1598828 bytes
total size: 2841968 bytes (88.3 kbit/s)
read 3706 symbols
entry point: 0x40000000
grlib> run
Booting Linux
Booting Linux...
PROMLIB: Sun Boot Prom Version 0 Revision 0
Linux version (root@brazilip-tec) (gcc version 3.2.2) #16 Mon Aug 20 19
:32:42 BRT 2007
Vendors Slaves
Ahb masters:
Ahb slaves:
0( 1: 1b| 0): VENDOR_GAISLER Unknown device 1b
+0: 0x0 (raw:0x3fff2)
+0: 0x80000000 (raw:0x8000fff2)
+0: 0x90000000 (raw:0x9000f002)
3( 1: 25| 0): VENDOR_GAISLER Unknown device 25
+0: 0x40000000 (raw:0x4003c002)
+1: 0xfff00100 (raw:0x10fff3)
Apb slaves:
+ 0: 0x80000100 (raw:0x10fff1)
+ 0: 0x80000200 (raw:0x20fff1)
+ 0: 0x80000300 (raw:0x30fff1)
+ 0: 0x80000400 (raw:0x40fff1)
+ 0: 0x80000500 (raw:0x50fff1)
+ 0: 0x80000600 (raw:0x60fff1)
+ 0: 0x80000700 (raw:0x70fff1)
+ 0: 0x80000b00 (raw:0xb0fff1)
TYPE: Leon2/3 System-on-a-Chip
Ethernet address: 0:0:0:0:0:0
CACHE: direct mapped cache, set size 8k
Boot time fixup v1.6. 4/Mar/98 Jakub Jelinek ( Patching kerne
l for srmmu[Leon2]/iommu
64MB HIGHMEM available.
node 2: /cpu00 (type:cpu) (props:.node device_type mid mmu-nctx clock-frequency
uart1_baud uart2_baud )
PROM: Built device tree from rootnode 1 with 918 bytes of memory.
DEBUG: psr.impl = 0xf fsr.vers = 0x7
Built 1 zonelists. Total pages: 64302
Kernel command line: console=ttyS0,38400 init=/sbin/init
PID hash table entries: 1024 (order: 10, 4096 bytes)
Todo: init master_l10_counter
Attaching grlib apbuart serial drivers (clk:80hz):
Console: colour dummy device 80x25
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
Memory: 252736k/262144k available (968k kernel code, 9244k reserved, 112k data,
116k init, 65536k highmem)
Mount-cache hash table entries: 512
checking if image is isn't (no cpio magic); looks like an initrd
Freeing initrd memory: 1561k freed
highmem bounce pool size: 64 pages
io scheduler noop registered
io scheduler cfq registered (default)
grlib apbuart: 1 serial driver(s) at [0x80000100(irq 2)]
grlib apbuart: system frequency: 80000 khz, baud rates: 38400 38400
ttyS0 at MMIO 0x80000100 (irq = 2) is a Leon
Loading theora ...
LEON THEORA driver by Andre Costa (2007) -
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
loop: loaded (max 8 devices)
RAMDISK: Compressed image found at block 0
VFS: Mounted root (romfs filesystem) readonly.
Freeing unused kernel memory: 116k freed
init started: BusyBox v0.60.5 (2007.08.04-05:15+0000) multi-call binary
Shell invoked to run file: /etc/init.d/rcS
Command: #!/bin/sh
Command: mount
Please press Enter to activate this console.
stopped at 0xf00140d0

Wednesday, 25 June 2008

Just benchmarked my first LEON3

29.8 Dhrystones MIPS! This is an 80MHz LEON3 system with no FPU. Onwards, to linux!

Monday, 23 June 2008

Just connected to my first LEON3 SoC

... via the JTAG debugger but I am still unable to drive the DDR due to the lack of DCM modules in this particular Xilinx. I am now turning my attention to the XUP board from Digilent as they are quite common around here.

Hopefully I shall get further down that road towards the goal of booting linux on the system....

Friday, 20 June 2008

Trouble with the ML403...

Heh, should have realised it wouldn't be that easy...

Basically the ML403 differs from the ML401 & 2 by the fact that they both their Virtex-4's have 8 DCMs as opposed the 403's 4, and the LEON3 core with a DDR controller (necessary for the built in DDR memory) needs 5. It took a surprisingly long time for me to realise that's what the error message meant. Still today has been quite productive with a lot of lessons learnt.

Another lesson is that Xilinx ISE on windows will rebuild a Xilinx ISE on linux project, meaning the 20 minutes I took building and routing the first design came to nothing, as the windows machine proceeded to take about 60 minutes to perform the same task.

Wednesday, 18 June 2008

Linux Tomorrow

I am borrowing a Xilinx ML403 board over breakfast (in exchange for some copper pipe) so I should be testing Linux on LEON3 tomorrow. I have also provided my MSc students a tutorial getting them off the ground in messing with GRLIB which I really need to write up in our knowledgebase.

grlib is proving quick to get off the ground, I just hope it proves easy to customize too.

GRLIB now compiling in ModelSim

After some silliness with the configuration stages GRLIB is now up and running.

First thing to do is informal validation tests against the various FPGA compilation tools we have available to see what produces working code, smallest/fastest etc.

Secondly I need to download Snapgear's linux for LEON3 and examine it for correctness / niceness. I might even port the patches into Angstrom and use that as a base depending on what I find.

Sunday, 15 June 2008

Final block of marking done....

Phew, glad that is over. Just got to set my MSc's going on their dissertations and help my Part III students get into and motivated over their projects.

I have given this lot of students as much feedback as I can, in an effort to improve things. A mark without comments is pretty pointless.

Platform express flow problems..

Interesting, we can get hold of Mentor's Platform Express from mentor, but not the seamless cve product that we need to simulate cores. That being said, GRLIB is looking like the only option at the moment.

Pity, however we may be able to extract a processor that we can trivially wrap for the Synopsys tool. ARMs have to be hardwired into IRQs and their bus selects however, which GRLIB seems to approach differently.

GRLIB on its own will probably be the best way, which is a pity as I think the Synopsys tools are great. Without a core and a bunch of licenses however we are not going to get very far.

Wanted: Alternatives to Design Compiler

There are only two synopsys licenses, which is far too few to teach with. I shall talk to Synopsys to see if I can get some more from them for teaching purposes.

As we have lots of Mentor licenses I shall investigate their products more.

Saturday, 14 June 2008

LEON3 as a core until we get an ARM

The SPARC v8 LEON3 and the associated GRLIB should fit in the planned teaching I have in mind:

It is what we needed: A core! It is also GPL licensed so we are legally entitled to and might be able to crack it open to better teach cache controllers and DMA controllers.

Thursday, 12 June 2008

esdsun4 now running

We are still using two old solaris workhorses: esdsun3 and esdsun4. Both are Enterprise 3500's with 6x 400MHz USII with 8MB of cache and a bunch of FCAL HDDs. Just got the second one working. What it troubling is that they are not much slower (if at all) than the V210's we have. Contrasting enterprise kit (old) with new budget kit doesn't reveal that many differences.

I am now Master of Masters!

Not as cool as it sounds, but I hope to do a good job. I now organize and manage the MSc summer projects.

Success targetting coreAssembler on FPGA

Just instantiated an AMBA bus structure into a cyclone III FPGA from Altera. Toolchain was a bit of a pain but most of that now sorted out. Now in a position to make arbitrary bus and peripheral structures. Just need cores now. And some form of memory.

coreAssembler -> Designware Compiler -> Quartus II

What a productive night.

Wednesday, 11 June 2008

Designware Compiler being difficult...

Trying to use Designware compiler to build for altera FPGAs.

Quartus II supplies the needed db files, however it doesn't seem to be consistent! I can't make any small designs, but I have successfully built a large AMBA structure for a cyclone II. Trouble is the libraries are rated as compatible with designware compiler 2004, not 2007.

The compiler dies with an internal error and a stack-dump. Will try driving design compiler by hand first to get more design information.

Tuesday, 10 June 2008

Sun saga continues

Tried my cunning plan. Completely failed to work.

New plan:

Install Sol9 and StorageTek SAN from scratch: a
Now all I have to do is:
  1. change vfstab
  2. change boot in eeprom
  3. boot to new disks
  4. move fiber
  5. setup mirrored root
  6. .....
  7. profit!!!!

Monday, 9 June 2008

Servicing Suns

I am trying to boot one of our cad servers from half of a mirror pulled from the other half. Predicatably it is being difficult, however if I want to preserve the exact setup I am at a loss how else to do it.

Still I think I am a sucker for punishment. Installing from scratch may, eventually, be the way to go from here.

The first batch of real exam marking this year

I have several thoughts for essential exam marking equipment:
  1. A stamp with a large red `?'
  2. Calming tablets
You need 1 when a student does a brain dump or creates an unconnected string of words. You need 2 when your paranoia increases as a student returns an answer that matches your perfect one. Luckily either extreme is rare, however they typically dominate the whole script.

First Post!

Heh, be warned, the humour of the above post is what you are likely to encounter here....