Wednesday, 3 February 2016

I have an honorable mention in the paper "Measurement scheme and analysis for weak ground state hyper fine transition moments through two-pathway coherent control"

Figure 7 from the paper showing the R.F. resonances in the cavity
This is a very interesting subject considerably outside my normal "comfort zone" but has led to some very interesting experimental work. My only participation is strictly on the experimental side - the theory is all the work of Mr. Choi, Prof. Elliott and the scientists before them.

Here is an "explain it like I am 16 attempt": The basic thrust of the work is to present a possible experimental apparatus to look at a property of cesium nuclei to measure an oddity that doesn't fit the main models of physics at the moment. In fact the behavior that has been measured is contradicted by other theories and absent from other experiments.

Nothing like resolving a contradiction. So some really nice fundamental stuff!

Link to the paper on The paper should be published in Physical Review A soon.

The authors are Jungu Choi and Prof. Daniel S. Elliott.

Saturday, 19 September 2015

Dr. Matthew A. Swabey - Resume / Curriculum Vitae

Quicklinks: Professional Career | Education | Current Teaching and Administration | Awards & Proposals | Industrial Activities | Papers & Articles | Skills & Experience | Professional Affiliations | Board Memberships | Previous Teaching & Administration

Professional Career

February 2011 – Present: Deputy Director of Instructional LabsECEPurdue University. Successfully negotiated a license and free fabrication on TI LBC7 BiCMOS for Purdue undergraduates (one of two in the world). Teaching an undergraduate project team that fabricates and tests custom mixed signal ARM® Cortex®-M0 SoCs. Developed an AMBA compatible DDR memory controller including analog IP for LBC7 using Denali memory IP. Developed various IP blocks around AHBLite. Developing analogue and mixed signal laboratory curriculum and facilities for three classes in ECE including EE Senior Design, a total of ~1000 students per semester. Managing a diverse team of three full time staff, temporary staff, ~20 teaching assistants and ~30 undergraduate lab assistants. Controlling budget spend of approximately $500k - $1million per year. Partnering with Dr. M. Johnson to run undergraduate ASIC mixed signal SoC design teams that fabricate and test custom integrated circuits as projects.
February 2009 - February 2011 (- Present as visitor): Researcher with the ARM-ECS Industry-University Center identifying and establishing relationships with ARM engineers, licensing IP, EDA tools and installing new flows. Established the Southampton/ARM secure research island. Assisted with the design, validation and DRC of the Tokachi-1&2 and Tokachi-3M TSMC 65nm research SoCs. Validated and tested the pre-release version of the ARM Cortex M0 DesignStart™ Processor. Personally taped out a simple ARM Cortex M0 IC to validate the core and our IBM® 8RF flow. Published a series of articles describing how to modernize and adapt the IBM PowerPC™ 405-FS simulation, verification and build scripts to modern EDA tools.
August 2007 – February 2011: Teaching Fellow, ECS, Southampton University. Employed at the same grade as a lecturer/instructor with a remit to innovate in teaching. Developed and delivered teaching in computer architecture, analogue electronics, electronic laboratories, C programming laboratories, DSP laboratories and managed all the MSc projects and dissertations. Developed microelectronic EDA flows and the cluster computing facilities to run them.
July 2006 – July 2007: Research Fellow, ECS, Southampton University. Researcher (Engineering and Physical Sciences Research Council (EPSRC) grant EP/E015522/1) extending the previous PhD studies into creating an OAE based biometric. Principle work areas were: systematic data collection, signal processing, the design and construction of novel very low noise analogue interface circuits and DSP software.
April 2005 – June 2006: Research Fellow, ECS, Southampton University. Researcher (EPSRC grant GR/S45324/01) responsible for specifying, designing and building the infrastructure for studying renewable energy management in suboptimal sites. The embedded system developed consisted of a Gumstix (an Intel XScale based single board computer running Linux) controlling a network of bespoke intelligent active energy monitors via an I2C bus.


School of Electronics and Computer Science (ECS), University of Southampton, UK:

2007 – 2008: Postgraduate Certificate of Academic Practice This is a Master’s level qualification (PG Cert) in teaching at University level. It focuses on the development of discipline-specific teaching and learning approaches alongside core competencies.
2001 – 2006: PhD titled “The Human Auditory System as a Biometric” This original research built on existing medical knowledge of otoacoustic emissions (OAEs). It required synthesizing a national medical dataset from separate studies and mathematically analysing it. Various parameterised identification algorithms were developed and an equal error rate of 1 in 1229 (0.0814%) was achieved. This was then verified against a smaller experimental dataset. A novel acquisition system was prototyped that improved on the existing medical systems by eliminating the requirement for a probe to be inserted into the ear canal. It used collector current tuned, discrete transistor ultra-low noise analogue designs.
1998 – 2001: Upper Second Class Bachelor of Engineering (Honours) in Electronic Engineering with a First Class for my final year project
Final Year Project: “Mobile Multichannel Telemetry System”. The project consisted of specifying the data capturing requirements and subsequently developing and designing the hardware and software for a multichannel, multi-rate data logger. A modular C system that compiled to a time-sliced program running on my custom board using a Microchip PIC17 with a 433MHz radio link to a PC was created.

Plymouth College, Ford Park, Plymouth, UK:

1992 – 1996:
A – Levels: Physics, Mathematics, Biology, General Studies
A/S – Level: Electronics
GCSEs: English Language & Literature, Mathematics, Physics, Biology, Chemistry, Electronics, Craft Design Technology, French, Latin

Current Teaching and Administration

Deputy Directory of Instructional Labs in ECE This is my present role and is covered above.
DL2 Laboratory Remodel One of the principle individuals involved in the $2.5 million dollar redesign of our current laboratory facilities to support approximately 50% of the ECE classes.
ECE 20700 Electronic Measurement Techniques This lab based course introduces and trains hundreds of students per semester in the use of essential electronic laboratory equipment. The learning context is realistic measurement situations and electronic constants.
ECE 20800 Electronic Devices and Design Laboratory This lab based course introduces the basic semiconductor devices from the p-n junction to the MOS transistor and finally the operation amplifier. Students have to design suitable bias circuits, verify and optimize them using SPICE.
ECE 40200 EE Design Projects This capstone course provides the essential ABET mandated senior design experience. Each semester requires the design of a technically challenging open-ended electrical-engineering project that will run each semester and then administrate and examine all the students.
ECE 49595 ASIC Fabrication and Test I & II The first semester of a two-semester sequence to give teams of 3 to 6 students the experience of designing an ASIC, having the chip fabricated, and testing it. The team of students will develop requirements for a design, prepare the design using VHDL, Verilog, create and use test benches to functionally verify the design, use automated tools to prepare a circuit layout, verify the final layout, submit the layout for fabrication, prepare a physical test bed, test or demonstrate the chip, and document all aspects of the design and test results

Awards & Proposals

Integrated Coherent Comb and Line-by-Line Pulse Shaper for RF Photonic Filtering (DARPA W3194Q-13-1-0018): Miniaturizing the existing Purdue development of 60GHz AWG technology developed by Prof. Andrew M. Weiner, Daniel E. Leaird and others.
HKN Turkey Contest Winner: Raised over $500 dollars for charity in competitive bidding on the understanding I would wear a Turkey Suit for a whole day, including teaching.
JISC Research Data Programme (call 07/09): Proposal submitted July 2009 for £200,000 to fund investigations into the preservation and visualisation of stored research data inside virtual machines.
JISC Information Environment and e-Research (call 12/08): Proposal submitted February 2009 for £310,000 to fund the creation of a virtual machine enhanced e-repository to contain machine images alongside existing document types.
Synopsys’ Charles Babbage Grant 2009: This was awarded to the School of ECS based on the proposal co-written by myself and Professor David Flynn, ECS & ARM.

Vice-Chancellor’s Teaching Award 2008: “ELEC2017/8 D2 Design Exercise: Engineering Chip Design (ASIC)”, this award is for ECS’s flagship ASIC design exercise taken by all year 2 electronics students in teams of 6. It is split into two parts: design and simulation, then after silicon fabrication (4 months), testing and evaluation.
Best Paper Prize ICBA 2004: “Using Otoacoustic Emissions as a Biometric”. This was the first paper published in this area on my research into using OAEs as a biometric characteristic

Industrial Activities

Cadence: Engaged in close collaboration to bring simple-but-good EDA flows targeting mature and advanced silicon nodes.
Texas Instruments: Successfully petitioned them to license their LBC7 BiCMOS process and related IP to allow Purdue undergraduates to experience a genuine CMOS design experience. I continue to work closely with their University team.
ARM: Worked on validating and testing a pre-release version of the ARM Cortex M0 DesignStart IP for University Access.
Spirax Sarco: Mentoring in a Knowledge Transfer Partnership on a research programme based around Texas Instruments' C5000 DSP hardware.
Roke Manor: Consulted about the feasibility of a multiprocessor system on chip core technology being considered for deployment in a new ASIC.
IBM and Synopsys: A series of articles describing how to modernize and adapt the IBM PowerPC™ 405-FS simulation harness and build scripts to the modern versions of Design Compiler and DFT Compiler.
D4 Technology: C# based PC interface software and C based ZigBee Microcontroller firmware (Texas Instruments CC2430) for the basestation of a multichannel 1400 node network.
ECS: A packet radio beacon based on a Microchip PIC16 transmitting a base station packet at regular intervals on 433MHz for calibration and system testing.

 Books, Papers & Articles

“Satisfying ABET criterion using an industrial Microelectronic Skills Incubator”Swabey, M.A. and Johnson, M., Microelectronics Systems Education (MSE), 2015 IEEE International Conference on, 2015.
“First Designs in Electrical Engineering”, Dimitrios P., Raghunathan N., Robinson B., Swabey M., Published Kendall Hunt 2015, ISBN 9780757593864
“Evaluation of otoacoustic emissions as a biometric”Grabham N.J., Swabey M.A., Chambers P., Lutman M.E., White N.M., Chad J.E. and Beeby S.P., IEEE Transactions on Information Forensics and Security, 2012, 8, (1).
“A comparison of verification in the temporal andcepstrum-transformed domains of transient evoked otoacousticemissions for biometric identification”, Chambers P., Grabham, N.J., Swabey M.A., Lutman M.E., White N.M., Chad J.E., and Beeby S. P., International Journal of Biometrics, 2011, 3.  
"IBM PowerPC™ 405-S: Getting started", a series of articles taking the CPU from RTL through synthesis to gate level verification, Swabey M.,, November 2009 – January 2010.
"The biometric potential of transient otoacoustic emissions", Swabey, M., Chambers P., Lutman M., White N., Chad J., Brown A. and Beeby S., International Journal of Biometrics, 2009, Vol. 1, No. 3.
"Innovative Teaching of IC Design and Manufacture Using the Superchip Platform", Wilson P., Wilcock R., Swabey M. and McNally B.I., IEEE Transactions on Education, Accepted for publication, February 2009.
"The Superchip: Innovative Teaching of IC Design and Manufacture", Wilson, P., Wilcock, R., McNally, B.I., Swabey, M. and Al-Hashimi, B., Custom Integrated Circuits Conference, September 2008, San Jose, CA, USA.
"IC Design and Manufacture for Undergraduates: Theory, Design and Practice", Wilson, P., McNally, B.I., Swabey, M. and Al-Hashimi, B., 7th European Workshop on Microelectronics Education, 28th May 2008, Budapest, Hungary.
"An Intelligent Fuse-box for use with Renewable Energy Sources integrated within a Domestic Environment", Wilson, P., Swabey, M., Brown, A. and Ross, J., World renewable Energy Congress, May 2005, Aberdeen, UK.
"Investigation into the Uniqueness of Neonate Transient Otoacoustic Emissions", Swabey, M., Beeby, S., Brown, A. and Chad, J., Acoustic Research Letters Online, October 2004, Vol. 5, No. 4.
"Using Otoacoustic Emissions as a Biometric", Swabey, M., Beeby, S., Brown, A. and Chad, J., Lecture Notes on Computer Science, July 2004, Vol. 3072.

Skills and Experience


Seven years of tutoring, lecturing, supervising projects and setting exams within Purdue (USA) and Southampton (UK) including invited participation in the software education working party and the analogue electronics working party. The working parties are tasked with improving student engagement and understanding in their respective areas.
Four years of postgraduate demonstrating within ECS including input into the structure and content of undergraduate electronic laboratories.
Provided reviews, guidance, advice and practical help to numerous third and fourth year undergraduate and MSc projects from 2001.

Management and procurement:

One of the drivers of the planning and design of space and facilities for approximately seven laboratory classes with a budget of $2.5 million USD.
Budgeting, staffing, fitting out with suitable lab equipment, software and consumables for eight Purdue Undergraduate Electronics Labs.
Deploying the Advanced Electronics Lab in ECS Southampton in 2008 to support cross departmental measurement and diagnostic work beyond the capabilities of individual research groups up to a frequency of 6GHz. This follows overseeing the commissioning of laboratories destroyed in the fire at Southampton in 2005.
Ongoing provision, licensing, installation and maintenance of part of the ECS CAD tool portfolio and IP portfolio (IBM, ARM, Cadence, Synopsys, Mentor Graphics, etc.).
Procurement and commissioning of a VMWare cluster, Linux servers and Sun CAD servers for research and teaching.
Production and maintenance of online (HTML/wiki) and print documentation.

Commercial and Industrial:

Established a strong relationship with Texas Instruments who are providing IP and microchip manufacturing for Purdue undergraduates for teaching purposes.
Established a strong working relationship with ARM and arm engineers enabling access to microelectronic IP suitable to pursue unique teaching opportunities.
Maintain Purdue’s relationship with Synopsys enabling access to pre-release tools, established through the Babbage grant, by creating material for their university curriculum and interacting with their engineers to integrate technologies into our courses where appropriate.
Maintained and extended the relationship with Imagination Technologies in Southampton involving them further in our undergraduate programme as a course sponsor and now a project sponsor. They are deploying their custom technology in our laboratories to enhance our MSc course in mobile electronics. ECS and Imagination are currently exploring joint research possibilities.


Prototyping Cadence Liberate flow to characterize analog IPs for use in the flow (IOs, DLLs).
Led an undergraduate team to develop a DDR memory interface on LBC7. Includes analog DLL and IOs. Testability, functional verification, verification IP and constraints were key.
Designed and implemented various HDL IP modules: ARM Cortex M0 Debug Unit, n-input transparent AHBLite bus matrix, ZBT synchronous SRAM controller, etc.
Designed and implemented power pads, corners and bi-directional IOs on TI LBC7.
Built EDA flows around IBM 8RF, TSMC 65nm using Chip-under-pad and Texas Instruments LBC7 BiCMOS. Included liaising with the MOSIS and Europractice MPW fab services.
Building prototype ARM based SoCs (a simple ARM Cortex M0 based prototype) and the Tokachi-1&2 multicore research SoCs.
Designing and automating repositories for IC design data using git and Subversion. Automation of EDA flows targeting mixed signal development using Python.
Experience with complete mixed signal design flow from specification to testing.
Successful mixed signal circuit designs built using radio modules.
Practical experience of hardware and software design for debugging.
Familiarity with Texas Instruments Code Composer and TMS320 DSP architecture.
Mixed signal design experience using Microchip PIC and Atmel AVR microcontrollers.
Verilog and System Verilog digital designs using Synopsys’ Design Compiler, Cadence Encounter, Synplicity Synplify (now Synopsys FPGA), Altera Quartus, Xilinx ISE and Mentor Graphic’s Modelsim/Questa.
PCB design and construction using Cadence Orcad tools and Altium Designer.
Extremely low noise audio frequency analogue circuit design using PSpice A/D.
Analogue CMOS CAD software Cadence Virtuoso (IC5 and IC6).


Microsoft Office to deliver teaching and presentations (PowerPoint), papers (Word) and financial activities (Excel).
LaTeX for larger documents such as theses and book drafts.
Extensive object oriented C++ experience including the standard template library.
Extensive C and assembler for paged/non-paged memory microcontrollers.
Matlab/Simulink and Octave mathematical languages.
Working knowledge of scripting languages: Python, Bash and (T)csh.
Experienced with the installation and management of Linux and Solaris CAD servers.
Proficient with Microsoft Windows 2000, XP and 7.
Previously maintained a Linux distribution for Sharp Zaurus PDAs (e.g. C760).

Professional Affiliations

Researcher at the ARM-ECS industry-university center, Southampton, UK
Member of the IEEE
Member of the Institution of Engineering and Technology
Fellow of the Higher Education Academy, UK

Board Memberships

Forum for Specification and Design Languages 2010, Local Technical Chair
Design, Automation & Test in Europe 2009, Chair of Local Organization Team (Technical Programme Meeting 2008)
11th IEEE European Test Symposium 2006, Local Technical Chair

Previous Teaching & Administration

Purdue University, USA

ECE 30600 Electronic Circuits and Systems Laboratory Experiments in electronic circuits and systems including spectral analysis techniques, sampling, distortion measurements, random signals, signal-to-noise ratio and correlation.
ECE 30800 Systems Simulation and Control Laboratory Instruction and laboratory exercises in the solution of differential equations that arise in the modelling of physical systems. Instruction in the principles of operation and design of linear control systems.
ECE 44000 Transmission of Information Analysis and design of Analog and Digital Communication Systems. Emphasis on engineering applications of theory to communication system design. The laboratory introduces the use of advanced engineering workstations in the design and testing of communication systems.

Southampton University, UK

MSc Microelectronics Systems Design Programme Leader While I held this role I was responsible for the academic content, admission requirements and day-to-day running of one of the two largest MSc programmes within ECS.
Co-supervisor of a PhD Project in an industrial collaboration with Spirax-Sarco developing novel DSP algorithms and the sensor/DSP platform to support them.
Supervisor of 4 MSc Projects in the area of computer architecture, developing RFID enhancements to commercial systems and robust, general purpose, SoC IP modules.
ELEC6003 & COMP6029 MSc Project Course Leader Aim: To maintain and improve the MSc support framework, handle mitigating circumstances cases and manage the running of all MSc programme projects.
COMP6009 Individual Research Project & COMP6033 Independent Research Review Course Leader Aim: To instil in students the essentials of credible academic research, i.e. evaluation of previous work, synthesis of work across a field and finally credible presentation of novel material. Also I ensured the annual student conference was an opportunity for them to practise essential research presentation skills in a realistic setting to our industrial partners.
ELEC3031 Analogue Electronics Course Leader Aim: To cover in some depth the mathematics and circuitry likely to be used between an analogue signal source and a digital signal processing system, making maximum use of available integrated circuits.
ELEC2013 Computer Systems Engineering Aim: To give understanding and context of modern processor architecture.
ELEC2018 Software Development Aim: To develop the needed skills to become a competent programmer for larger software projects.
COMP1010 ‘C’ Programming Laboratories Aim: To provide the student with the necessary skills to write C programs for PCs and microcontrollers.
ELEC1013 Introduction to Digital Electronics Laboratories Aim: To provide a background in digital electronics to computer science students

Wednesday, 1 July 2015

Workshop Presentation from DAC2015: A Holistic Platform for Education in ASIC Design & Manufacturing

I was fortunate enough to be invited by Cadence to present at a Workshop 9: Interdisciplinary Academia Industry Collaboration Models and Partnerships at DAC 2015 in San Francisco.

Here is the presentation I gave, "A Holistic Platform for Education in ASIC Design & Manufacturing" on our current work with undergraduates on SoCs.

Thursday, 5 March 2015

Improving an LM318 Op-Amp Follower by Prototyping Techniques

LM318 schematic for fast follower operation
This little exercise came from trying to make a differential NTSC video sender over CAT5 twisted pair from discretes (I know - don't do this at home, just get an IC that does this for you like the MAX4447 / MAX4146 pair).
Throughout this article I will be making liberal references to the online free book "Op-Amps for Everyone" Texas Instruments Document SLOD006B by Ron Mancini.
The Op-Amp I decided to base the design around (again there are discrete transistor versions of this circuit that are more capable than this) is the incredibly venerable LM318.
Its main specs are:
  • Small Signal Bandwidth . . . 15 MHz Typ.
  • Slew Rate . . . 50 V/µs Min
  • Bias Current . . . 250 nA Max (LM118, LM218)
  • Supply Voltage Range . . . ±5 V to ±20 V
  • Internal Frequency Compensation
 [The LM318 is a pretty incredible design for its age - it really is! Especially since high performance PNP transistors were simply not available. For more details please see p19 of "IC Op-Amps through the ages" by Thomas H. Lee, 2000 rev. 2002]

The circuit I am trying to build is from the datasheet as a "fast follower" using lead compensation (SLOD006B section 7.6) and built on a standard prototyping board (called a breadboard at times).

Attempt 1: Standard Prototype Board

[Note: Bypassed both supplies with 0.1µF and 1µF ceramic capacitors.]
Stimulating with a 1V Pk-Pk sinewave swept from 1MHz to 20MHz we should see the perfect flat gain of 1 till approximately 15MHz. Of course, we don't!
The gain peaks at approximately 2MHz at about 3 and then crashes to zero. The good news is that I have seen this behavior before and it is particularly well explained by SLOD006B section 7.7. Stray capacitance on the inputs. On a standard breadboard the stray input capacitance between V- and V+ is a minimum of 2pF. A good discussion on this can be found on EEVBlog #568.
First - to the simulator! Now SPICE is brilliant. Models of Op-Amps are not, and vary from modelling just the gain and frequency rolloff to full with major parasitics and noise sources depending on part and manufacturer. However if the SPICE model behaves the same with appropriate parasitics added it can confirm the behavior:
SPICE Frequency Response of the LM318 "Fast Follower" with a 10pF parasitic wired between V+ and V-
 This is a pretty damn good match to the observed behavior.

Attempt 2: Partial Air-Wire

[Refer to Linear Technologies App Note 47 p27 - a legendary app note, you should read the whole thing!]

Partially Air Wired LM318 "Fast Follower" with V+ soldered directly to the input 10k resistor and compensation pins lifted

The results of this approach was a massive improvement. The peak in the gain has smoothed out and I can sweep the stimulus (1V Pk-Pk sinewave) from 1MHz to 11MHz before the gain is 50%. The gain now peaks at approximately 2 around 6MHz.

Attempt 2: Full Air-Wire

In an effort to eke out further improvements the circuit was built fully air wired. I cannot emphasize the importance of removing ALL traces of glue and flux from around the pins of the Op-Amp.
Fully Air Wired LM318 "Fast Follower". [Note that the test configuration did not use the yellow crocodile clip lead to inject the signal and all grounds were brought together in the loop at the top right.]
Results from this approach were a further improvement of approximately 20% with the gain peaking at around 1.8 at 8MHz and the 50% point pushed out to 13MHz.


I have a feeling that to improve linearity it would be worth me building a circuit with a gain of 2V/V. From reading Op-Amps through the ages it seems that this design was not optimized as a follower and in fact the datasheet contains dire warnings of trying to build it without resistors and a compensation capacitor in the feedback loop.
I am continually impressed by the Op-Amp designers of old who were able to make these high performance circuits with pathetic silicon technology and little to no simulation support. I shall revisit this article and capture some more scientific measurements at a future date.

Thursday, 4 December 2014

Buffalo Linkstation LS-XHL as a bitorrent sync node

A long time ago I bought an LS-X1.0TL Linkstation Pro (LS-XHL) from Buffalo.  The reason I (and
many others) bought it is that it is an 1.2GHz Marvell ARMv5 with 256MB of RAM, a SATA connection, a USB 2.0 port and a gigabit wired ethernet port that you can run linux on. All for about 20W.

The great news is that dusting it off after finding it in a box I find that it is better supported than ever! There is a standard Debian wheezy disk image and kernel 3.14.4 without patches running on the SoC.

Obviously the best use is to install Bitorrent Sync on it and hide it on another network at a different physical location to provide an extra node for security and bandwidth! (grin)

Here is how I did it (based on the work of fjen from, original threads here and here and the lsmonitor script fix is based off Dennis82's post).

1. Cracking the case: Really don't try this without seeing the video - I broke quite a lot of my case getting it open before this existed.

2. Extract the hdd and connect it to a linux system or a linux VM (this is very hard to do on windows). Using dmesg or similar locate the disk device node, e.g. /dev/sdb. Make sure you have the right disk or you might destroy your operating system hard drive.

3. Change the disklabel to GPT (GNU parted)
3.1 Create primary partition 1 at 0 to 128MB, type ext3
3.2 Create primary partition 2 at 128MB to -1024MB (yes -1024MB), type ext4
3.3 Create a swap partition 2 at -1024MB to -1s, type Linux swap

4. Format the filesystems (replace X with the letter of the ls-xhl hard disk you found earlier):
4.1 mkfs.ext3 /dev/sdX1 (the boot partition of 128MB)
4.2 mkfs.ext4 /dev/sdX2 (the main filesystem partition)

5. Mount the filesystems somewhere convenient (as root):
5.1 mkdir ls-xhl_img
5.2 mount /dev/sdX2 ./ls-xhl_img
5.3 mkdir ls-xhl_img/boot
5.4 mount /dev/sdX1 ./ls-xhl_img/boot
5.5 check that ls ./ls-xhl_img shows "boot"

6. Download the wheezy root filesystem from
6.1 Unpack as root using GNU tar to the ls-xhl_img/ directory (not boot/)
6.2 Unmount the partitions (ls-xhl_img/boot first)

7. Install the hard drive back onto the ls-xhl's circuit, connect the ethernet cable to a network with a DHCP server where you can find the logs (your home router typically has a page in the web interface where you can find the DHCP logs) and power on.
7.1 The LED on the front should blink blue for a while before going solid on.
7.2 Check the DHCP logs for the IP address that the LS-XHL has acquired using the name linkstation.

8. ssh into that IP address as root (password toor) and run the following commands:
dpkg-reconfigure locales
dpkg-reconfigure tzdata
rm /etc/ssh/ssh_host_* && dpkg-reconfigure openssh-server
apt-get update

8.1 Install the debian updates to ensure you have a safe, secure system.

9. Update the kernel:

10. Update the lsmonitor script in /etc/init.d/lsmonitor included at the end  (thanks Dennis82 for the pointer to this solution).
10.1 Install the following packages: apt-get install hddtemp lm-sensors fancontrol
10.2 Restart the lsmonitor script by /etc/init.d/lsmonitor restart 

11. Create a user called btsync (or similar) to own the btsync processes and disk space for files.
11.1 Install Bitorrent Sync server packages using the unoffical .deb packages from here:
11.2 Configure packages to run as user btsync.
11.3 Direct your web browser to the IP address:8888 and the Bitorrent Sync GUI should greet you.

12. Profit!


# Provides:          lsmonitor
# Required-Start:    $syslog
# Required-Stop:     $syslog
# Default-Start:     2 3 4 5
# Default-Stop:      0 1 6
# Short-Description: Monitor Linkstation LS-CHLv2 and LS-XHL
# Description:       Enable service provided by daemon.

# lsmonitor:
# - handle ls complete power-on
# - monitor hdd temperature & control fan speed
# - monitor hdd status & contol function led
# - monitor function button (todo)
# - monitor power switch (todo)
# Changelog:
# - Modified to work with a Debian kernel on a LS-CHLv2
# - Added hdd status monitoring
# - Modified to work with a vanilla kernel >= 3.6
# - Modified to work with a vanilla kernel >= 3.8
# Copyright (C) 2013 Sergej Wildemann
# Based on:
#  blstools - Copyright (C) 2010 Michele Manzato
# Credits:
#  Thanks to archonfx on Buffalo NAS Central forum for HDD
#  temperature monitoring command.
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# GNU General Public License for more details.

# Location of pid file

# Control interfaces


# Fan speeds

# HDD temperature limits for fancontrol

# Load settings
. /etc/default/lsmonitor

# Set and get current fan speed
 if [ $1 = "get" ]; then
  cat $FAN_INPUT
 elif [ $1 = "set" ]; then
  echo $2 > $FAN_TARGET

# Monitor HDD temperature & control fan speed
 # Retrieve HDD temp
 HDDTEMP=$(smartctl /dev/sda --all | awk '$1 == "194" {print $10}')

 # Change fan speed accordingly
 if [ $HDDTEMP -le $HDDTEMP0 ]; then
  fan_speed set $SPEED_STOP
 elif [ $HDDTEMP -le $HDDTEMP1 ]; then
  fan_speed set $SPEED_SLOW
 elif [ $HDDTEMP -le $HDDTEMP2 ]; then
  fan_speed set $SPEED_HIGH
  fan_speed set $SPEED_FULL

# Monitor HDD status and deactivate power led if idle
 HDDSTATUS=$(hdparm -C /dev/sda | grep "standby")
 if [ -z "$HDDSTATUS" ]; then
  echo default-on > $LBFUNC/trigger
  if [ $HDDSTATUSOLD -eq 0 ]; then
   echo `date` active >> /var/log/hddstatus.log
  echo none > $LBFUNC/trigger
  if [ $HDDSTATUSOLD -eq 1 ]; then
   echo `date` standby >> /var/log/hddstatus.log

# Control LS switch status to power down the unit

 echo 1 > $FAN_CTRL/pwm1_enable

 fan_speed set $SPEED_STOP

 while [ true ]; do
  # Check switch status
  #PWR_SW=`cat /sys/class/gpio/gpio${GPIO_PWR_SW}/value`
  #AUT_SW=`cat /sys/class/gpio/gpio${GPIO_AUT_SW}/value`

  # Check HDD status

  # Terminate when in OFF state
  #if [ "$PWR_SW" -eq 1 ] && [ "$AUT_SW" -eq 1 ]; then
  # break

  # Once per minute monitor HDD temperature
  if [ $COUNT -eq 12 ]; then
   COUNT=$(( $COUNT + 1 ))

  sleep 5

 # Run the fan at low speed while halting, just in case halt hangs the unit
 fan_speed set $SPEED_LOW

 # blink power led
 echo timer > $LPOWER/trigger
 echo 100   > $LPOWER/delay_on
 echo 100   > $LPOWER/delay_off

 # Initiate unit shutdown

# Kill the lsmonitor daemon
 if [ "$PID" != "" ] ; then
  kill $PID

case $1 in
  # Start the lsmonitor daemon
  lsmonitor_daemon &
  echo $! > $PIDFILE
  # Kill the lsmonitor daemon

  $0 stop && sleep 2 && $0 start

  echo "Usage: $0 {start|stop|restart}"
  exit 2

Thursday, 2 October 2014

Modding a Lattice CPLD ispMACH 4256ZE breakout board for an external clock

4256ZE Breakout Board with CLK PCB Operating
Taking a quote from the Lattice website this board is probably the best way of getting started with a CPLD I know of with 5V tolerant I/Os:

"The ispMACH 4256ZE Breakout Board is a simple, low-cost board that provides convenient access to densely-spaced IOs. Each I/O on the device is connected to 100-mil header holes. By adding test probes, jumper wires, or pin headers to the board, you can easily evaluate function and performace of the IO cells of the ispMACH 4256ZE."

The only issue I have with this board is that unlike its more modern version, the MachXO2 Breakout Board (note that its IOs are only 3.3V tolerant), it has no site for an external clock crystal on the PCB. This means you are limited to the internal 5MHz oscillator. Or not if you are clever and have access to PCB design software and are willing to spend $1 with OSH Park community PCB service.
The Oscillator series chosen for this project was the Fox FXO-HC53 series, a SMT crystal measuring 5mm by 3.2mm. Since this chip doesn't support LVDS we are using a HCMOS output. The two speeds chosen were 80MHz and 200MHz.
Note the oscillator is specified to drive up to 15pF and a CLK input pin on the ispMACH 4256ZE is 6pF max. The traces on the board are going to contribute further capacitance but it should be within spec.

The board design is detailed below:
CLK Board Schematic

The PCB design has a few features that are worth noting:
  • The output pin of the oscillator is placed as close as possible to the output pin hole and the ground pin hole is as close as possible to the ground pin of the oscillator. This is to minimize impedance and coupling of the high frequency on the board.
  • There are two ground pins - one for the power supply and the other for the CLK return current to make it easier to interface.
  • A pullup resistor 0805 position is available in case the internal pullup proves insufficient or a different crystal is chosen.
  • The footprint of the crystal has the pad size extended outside the normal footprint by twice the length to allow manual soldering.
  • The power and output pins are in a row on a 0.1" spacing to allow compatibility with standard prototyping boards and systems.
  • The bottom of the board under the crystal and high frequency traces is one large ground plane.
  • Total board size is 525mil x 375mil.
CLK Board Top Layer

CLK Board Bottom Layer (Text not reversed)

OSH Park Rendering of the Manufactured PCB

Wednesday, 17 September 2014

Installing LaTeXML into a local directory...

I have been working for a while on a document management system that will use MathJax and .tex inputs to create pretty PDF output and good websites.

Researching the available converters the one that is most attractive and most maintained is LaTeXML.

Firstly I have to setup perl to install packages locally for me to use:

export PERL5LIB=~/perl5/lib/perl5
export PERL_MB_OPT="--install_base '$HOME/perl5'"
curl -L | perl - -l ~/perl5 App::cpanminus local::lib 

I now have to fetch and install LaTeXML:

cpanm --force
Note that you will need the prerequisite system libraries installed onto the system - this approach doesn't provide copies of LibXML etc. as needed.

Command lines:
latexml --dest=example.xml example.tex
latexmlpost --format=html5 --javascript='../MathJax_down/MathJax.js?config=TeX-AMS-MML_HTMLorMML' --destination=example.html example.xml
The results are really quite impressive - no links yet as they are behind our 'paywall' but hopefully soon.