Synopsys Designware System Level Library Compiled

Rebuilding everything from scratch with a clean install, and setting the following environment variables:

CC /usr/local/gcc/3.3.6/bin/gcc
CXX /usr/local/gcc/3.3.6/bin/g++
LD /usr/local/gcc/3.3.6/bin/g++

and look

Synopsys DWSLL still won't compile even with gcc-3.3.6 [FIXED]

[see above post, must have had a broken systemc install left lying about]

Having built a version of gcc-3.3.6 that compiles correctly and passes the tests I now get a new (and unpleasant) build error:

/usr/local/gcc/3.3.6/bin/gcc  -o .vptest//linux/dwsll/gcc-3.3.6/osci-2.2.0/vptest .vptest//linux/dwsll/gcc-3.3.6/osci-2.2.0/CoreManager.ctor.o .vptest//linux/dwsll/gcc-3.3.6/osci-2.2.0/IntCtrl.ctor.o .vptest//linux/dwsll/gcc-3.3.6/osci-2.2.0/MuxRoutingView.ctor.o .vptest//linux/dwsll/gcc-3.3.6/osci-2.2.0/Tester.ctor.o .vptest//linux/dwsll/gcc-3.3.6/osci-2.2.0/UART.ctor.o .vptest//linux/dwsll/gcc-3.3.6/osci-2.2.0/powerDashboard.ctor.o .vptest//linux/dwsll/gcc-3.3.6/osci-2.2.0/registerView.ctor.o .vptest//linux/dwsll/gcc-3.3.6/osci-2.2.0/vptest.o .vptest//linux/dwsll/gcc-3.3.6/osci-2.2.0/vptest_sc_main.o .vptest//linux/dwsll/gcc-3.3.6/osci-2.2.0/VT100.ctor.o -L/opt/fastcad/software/synopsys/linux/dw_sys-l-lib_2008.12/linux/dwsll/gcc-3.3.6/osci-2.2.0/lib -llt-O -g -fPIC -Wl,-Bsymbolic   /opt/fastcad/software/synopsys/linux/dw_sys-l-lib_2008.12/linux/dwsll/gcc-3.3.6/osci-2.2.0/lib/snps_tlm.a -L/opt/fastcad/software/synopsys/linux/dw_sys-l-lib_2008.12/linux/dwsll/gcc-3.3.6/osci-2.2.0/lib -L/opt/fastcad/software/systemc/systemc-2.2.0/lib-linux -L/opt/fastcad/software/synopsys/linux/dw_sys-l-lib_2008.12/linux/dwsll/gcc-3.3.6/osci-2.2.0/../runtime/Shared/Debuggers -lpthread -lsystemc -lqt-mt -lvdidll -ldl -rdynamic /opt/fastcad/software/synopsys/linux/dw_sys-l-lib_2008.12/linux/dwsll/gcc-3.3.6/osci-2.2.0/lib/libsimdll.a 2>&1 | c++filt
/opt/fastcad/software/synopsys/linux/dw_sys-l-lib_2008.12/linux/dwsll/gcc-3.3.6/osci-2.2.0/lib/snps_tlm.a(simlog.o)(.text+0xc88): In function `Simlog::Abort(IUnit*, char const*, ...)':
: undefined reference to `typeinfo for unsigned'
/opt/fastcad/software/synopsys/linux/dw_sys-l-lib_2008.12/linux/dwsll/gcc-3.3.6/osci-2.2.0/lib/snps_tlm.a(snps_tlm_imemory_tlm2.o)(.gnu.linkonce.r._ZTIPN8snps_tlm20vre_config_extensionE+0x0): undefined reference to `vtable for __cxxabiv1::__pointer_type_info'
/opt/fastcad/software/synopsys/linux/dw_sys-l-lib_2008.12/linux/dwsll/gcc-3.3.6/osci-2.2.0/lib/snps_tlm.a(snps_tlm_manager.o)(.text+0x3aa5): In function `snps_tlm::manager::SimMain()':
: undefined reference to `typeinfo for int'
/opt/fastcad/software/synopsys/linux/dw_sys-l-lib_2008.12/linux/dwsll/gcc-3.3.6/osci-2.2.0/lib/snps_tlm.a(snps_tlm_manager.o)(.gcc_except_table+0x48c): undefined reference to `typeinfo for int'
/opt/fastcad/software/synopsys/linux/dw_sys-l-lib_2008.12/linux/dwsll/gcc-3.3.6/osci-2.2.0/lib/snps_tlm.a(snps_tlm_manager.o)(.gnu.linkonce.r._ZTIP15ManagerListener+0x0): undefined reference to `vtable for __cxxabiv1::__pointer_type_info'
/opt/fastcad/software/systemc/systemc-2.2.0/lib-linux/libsystemc.a(sc_main_main.o)(.gcc_except_table+0x38): undefined reference to `typeinfo for char const*'
collect2: ld returned 1 exit status

Synopsys Innovator and Designware System Level Library II

More things to do with Synopsys Designware System Level Library.

Just so you know:

When they say use gcc-3.3.6, they mean gcc-3.3.6. RHEL3 shipped with gcc-3.2.X and RHEL4 with gcc-3.4.X. Both build models without errors but when executed segfault.

I am building a copy of gcc-3.3.6 now following this excellent guide by Tellurian.

More to follow.

MSc Dissertation Titles for 2009

1. An OpenSPARC with Hypertransport
Add a memory mapped Hypertransport port to an OpenSPARC processor.

2. SystemC to Reality
Take the Synopsys innovator SystemC based example of an MP3 player and
convert as much as possible to real hardware to assess the accuracy of
the Virtual Platform Model using the EVE accelerator.

3. Accelerating Geometric Mathematics
Taking the departments Geometric Maths co processor design and attaching
it to an IBM PowerPC 405 processor (either memory mapped or via the
coprocessor port) as efficiently as possible.

4. Hardening Soft Cores, the advantages and problems
Take the LEON3 opensource Sparc v8 processor and the IBM PowerPC 405
processor softcores (one is VHDL, one Verilog) and study them for speed
and size optimisations using blocks inside an FPGA like embedded
ram/multipliers. The LEON3 is already optimised and will serve as an
example.

5. Bi-width Processing for Sensor Applications
Research and design a processor with 2 data word widths - 8bits for low
power mode and an additional 32 bits when turned into high power mode.

Research the LEAP architecture first and try to improve it.