DATE09 TPC finished and went well - linksys WRT54GLs are awesome!

Arrived at the IET on the evening of Wednesday with my team this week and immediately got the benefit of the IET's professional staff. Within 1 hour I had the server running a custom software package crafted specifically for DATE to manage the submissions.

Imagine trying to manage 900 submissions on paper + email? Impossible.

In the initial hour I also deployed 4 wifi routers, all linksys WRT54GL's to manage the 190 members who review the papers in groups organised by topics.

On Thursday under peak load the WRT54GL's were handling 43 WPA encrypted connections simultaneously (note that the SPI was disabled and also note a CPU monitor would be very helpful to gauge the CPU load).

They worked all day with only 5 laptops unable to connect, and considering the fact that wifi with encryption isn't a very well adhered to standard (lots of bugs) that is just noise. Even that was resolved with a driver update to a 2200BG card from Intel.

It all had to work, and it all came together.

Synopsys Babbage Grant Proposal In!

It has been a most incredible slog getting the grant proposal out of the door. But now it is all done and I am really thankful. DATE2008 TPC here I come.

The love affair with freenx is over.... time to make the marriage work

It seems that not much survives contact with students!

Basically if the freenx session isn't correctly terminated or established then desktop processes and a nx process are left running to the server which will prevent them logging in again.

However I am not the first person to notice this:

PSI Labs who use the technology have developed a RPM of scripts to manage this properly called nxcleanup. A user session has the standard number of processes for the desktop however there is an associated nx process that the student doesn't own. So the script nxclean would need to be run as root.

How do I enable a student to run a script as root that wipes out processes of an arbitary user?

Simple: Use a setuid "shim"! Write a trivial C program that takes no inputs (or has very, very thorough sanity checking!) which identifies the current user using posix calls and then exec's the script after passing it the current username. Nifty eh? This is a standard way of making scripts run safely as root. I'll post it as soon as I am done.

NX Technology Makes Remote X Possible

I implemented NX technology on our linux CAD servers some time ago.

NX has enabled a whole distance learning class from America using some really poorly coded CAD tools (some are windows GUIs run under emulation).

It made it like using them over the LAN!

If you have remote UNIX application needs then please consider this technology.

I am more than happy to consult on your CAD architectures.

AVR Studio and WinAVR as C teaching tools...

AVR Studio when run in combination with WinAVR (packaging avr gcc, avr-libc and all the other gubbins) provides an awesome 1st learning environment for people learning C for the first time

• Completely free, for students and staff
  
• Traffic light graphical message highlights: Green spots next to messages when things went right, yellow for warnings and red for errors. Instantly understandable!
• Graphical indication of the current location in the program with autostep to move step by step through the program - outlines the flow immediately.
• Processor window showing the program counter, cycle counter (how much time has your program taken?). Turning ints to floats added 4000 cycles to a simple test program.
• Internal processor registers very visible
• I/O View graphically highlights ports and pins with a row of 8 squares which are filled when the bit is set. Instant graphical Hex to Binary

I really think that this is an ideal learning environment, not too big and not too small.

Router Resurrection....

Just fixed a Linksys BEFSR41 v2. Seems that the power brick had a standard cylinder DC plug however the central bore was about 1mm larger than the socket's central pin. I originally thought that I just had a 3rd party powerbrick, however a colleague of mine recognised the router and explained that it was a similar problem for him. Maybe a dodgy batch? Anyway the DC socket was a standard part, the warranty was void through age anyway so a cheap replacement, £1.11, has fixed the problem.

Better than new.

Firefox disrespecting your download preferences on MacOSX?

On OSX (Apple Macintosh Leopard, 10.5) does firefox ignore your download directory and constantly dump files on the desktop? Does your desktop get incredibly cluttered?

In all likelihood you have updated to the version of OSX you have now. And it has left behind a piece that is ruining your day: ~/Library/Preferences/com.apple.internet.plist

Copy this to your Desktop, download something and test it out. You should suddenly find that the firefox is honoring its preference.

ESSCIRC Summary...

Sorry for the lack of daily updates. What can I say? Every day was an 8:30 start, finishing at 18:00 sometimes. This is without anyone leaving in the sessions I was in, which if you have ever been to a conference is really unusual.

An interesting combination of academic, student and company presentation. Interestingly the companies typically showed much more finished products.

Anyway it was really well worth the visit (not to mention the whiskey tasting or the visit to murrayfield....)

Cadence Encounter SEGV on start faults cured III

It is the fonts. I had similar segv crashes using X on windows without the fixed and misc fonts installed. Seems Cadence likes its traditional X client setup. Now I just need to diagnose what font packages I haven't installed / installed in the wrong places.

Day 1 Done

I particularly liked the plenary Technology Interfacing for Fabless Semiconductor Companies by
Vahid Manian. For those who don't know he works for Broadcom. It was really interesting hearing how they manage their relationships with the CMOS foundries and how much effort they put into owning their own cell libraries and techniques.

More to follow....

Catch up with me at ESSCIRC next week

ESSCIRC 2008, Edinburgh. I am really looking forward to this conference, and I am meeting up with Cadence and NMI to discuss the Cadence Academic Network. Should be good.

Look out for me with a badge from Southampton University.

Are you and academic and thinking of buying a Xilinx development kit?

Then I can't plug Digilent enough. They have two very large FPGA boards available for very keen prices. The first is the Xilinx XUP, which is a XC2VP30 Virtex 2 Pro with 2 405PPC cores. This board supports DDR and is a great way to get started with prototyping Gaisler SoC designs. The excellent academic price is only $299! One word of warning: this board doesn't have true SATA ports depite there being connectors and labels saying SATA. They are high speed digital data links that are SATA like but are SATA non-standard and cannot connect to a SATA HDD. No out of band signals.

The second is an uprated ML505. This is identical to the standard Xilinx ML505, but it has a much larger FPGA on it (XC5VLX110T) and comes with a JTAG programmer. The ML505 from Xilinx doesn't. Total price $750.

I have hunted about and the prices here end up hundreds of pounds less than full commercial prices. In the case of the ML505 it is about £300.

Why getting a linksys WRT54GL wireless router is a good idea...

Basically, the WRT54G router is now on the 8th revision of the hardware and has had it's software updated since it was made. For example the current software set can have its web management software secured with SSL and supports WPA/WPA2, concepts that didn't exist when they started making the model.

Also if you need to do something really special you can remove the stock firmware and replace it with OpenWRT linux, almost limitlessly configurable. One point: the linux compatible version is sold separately these days as the WRT54GL

Just P&R'ed and unconstrained SoC using Cadence Encounter

Excellent, a LEON3, DDR controller, misc peripherals using a ST Microelectronics 120nm process from CMP. It was badly done, unconstrained and in all likelihood completely non-functional but it is a real start.
Taking it forward:

1. Verifying the rc generated verilog netlist is functionally correct. Modelsim will work for us here.
2. Using rc to generate the netlist from two technology files: Low Leakage and High Speed to allow the critical path to run faster.
   
3. Generalizing the setup of Encounter such that it fully uses the whole designkit in an easy-to-use package.
   
4. P&R'ing a whole SoC.
5. Verifying the back-extracted layout is fully correct.
   

Cadence Encounter SEGV on start faults cured II

New diagnosis: The problem occurs when it attempts to display the window on Fedora Core 8 with or without compiz. I wonder if it ever worked? New cure: SEE LATEST POST ON THIS

xorg-x11-server-Xorg-1.3.0.0-47.fc8
Linux **** 2.6.25.14-69.fc8 #1 SMP Mon Aug 4 14:00:45 EDT 2008 x86_64 x86_64 x86_64 GNU/Linux

Dump of problem:

encounter
This version requires license using cdslmd daemon.
Checking out Encounter license ...
SOC_Encounter_GXL 6.2 license checkout succeeded.
INFO: Current OA version selected: OA22
Starting console server on port esdcad4.ecs.soton.ac.uk:8888 ..
sourcing /home/esdcad/software/cadence/linux/soc62_USR4/tools/fe/etc/rdaDSL.tcl
*******************************************************************
*   Copyright (c)  Cadence Design Systems, Inc.  1996 - 2007.     *
*                     All rights reserved.                        *
*                                                                 *
*                                                                 *
*                                                                 *
* This program contains confidential and trade secret information *
* of Cadence Design Systems, Inc. and is protected by copyright   *
* law and international treaties.  Any reproduction, use,         *
* distribution or disclosure of this program or any portion of it,*
* or any attempt to obtain a human-readable version of this       *
* program, without the express, prior written consent of          *
* Cadence Design Systems, Inc., is strictly prohibited.           *
*                                                                 *
*                 Cadence Design Systems, Inc.                    *
*                    2655 Seely Avenue                            *
*                   San Jose, CA 95134,  USA                      *
*                                                                 *
*                                                                 *
*******************************************************************

@(#)CDS: First Encounter v06.20-s285_1 (32bit) 03/20/2008 18:59 (Linux 2.4)
@(#)CDS: NanoRoute v06.20-s222 NR080304-1637/USR54-UB (database version 2.30, 58.1.0) {superthreading v1.10}
@(#)CDS: CeltIC v06.20-s075_1 (32bit) 03/06/2008 22:51:18 (Linux 2.4.21-37.ELsmp)
@(#)CDS: CTE v06.20-s256_1 (32bit) Mar 20 2008 15:56:31 (Linux 2.4.21-37.ELsmp)
--- Starting "First Encounter v06.20-s285_1" on Thu Sep  4 15:05:31 (mem=62.9M) ---
--- Running on esdcad4.ecs.soton.ac.uk (x86_64 w/Linux 2.6.9-78.0.1.ELsmp) ---
This version was compiled on Thu Mar 20 18:59:03 PDT 2008.
Set DBUPerIGU to 1000.
Set Default Mode Capacitance Scale Factor to 1.00
Set Detail Mode Capacitance Scale Factor to 1.00
Set Coupling Capacitance Scale Factor to 1.00
Set Resistance Scale Factor to 1.00
Set net toggle Scale Factor to 1.00
Set Shrink Factor to 1.00000
Encounter terminated by internal (SEGV) error/signal...
*** Stack trace in log file.

Cadence Encounter SEGV on start faults cured

Problem: On RHEL 4u7 encounter from soc52 and soc62 crashes with a SEGV on run. In the stacktrace are lots of Tcl type errors.

Solution: Install RHEL 3! Seriously, running the most supported OS, in this case RHEL 3, solved the problem.

Cadence rc LEON3 compilation success

I have just used Cadence SoC's rc (RTL Compiler) to build a verilog netlist of a LEON3 SoC. The estimates are that it would run at 300MHz on a 120nm process.

Now I just need to progress getting it into encounter to start floorplanning. And a large amount of verification and checking that it is valid and correct.

Cadence Physically Knowledgeable Synthesis on solaris

Running a very old version of cadence pks_shell I decided to play about a bit with the configuration of the two old sun E3500's. Basically the systems are old 6 processor UltraSPARC II's and I had split the memory between them evenly. This turned out to be a very silly thing to do! It meant I didn't take advantage of the fantastically wide interleave available: If I install 4 lots of 1GB then I get a 4 way interleave quadrupling the memory bandwidth. So I am timing the compile again. Unfortunately our Cadence licensing doesn't allow me to share benchmark information, but it is surprisingly quicker.

Final flow looking better already: Cadence rc

After a lot of checking about it seems SoC Encounter comes with its own RTL compiler which is a lot more modern than our installed version of PKS. It also looks like a lot of the functionality of PKS was pushed into encounter which is the sensible place for it to be. When laying out a modern SoC with IP blocks, analogue and RTL it makes sense to do the floorplanning, clock tree balancing and reordering all in one tool.

Converting Libraries for use in Cadence PKS

Our designkits (which shall remain unspecified except that you can get some of them from CMP) mainly support Synopsys tools. However we have limited licenses for Design Compiler so to use them in Cadence PKS you can use a nifty little program called syn2tlf. This converts .lib files to .tlf, used by Cadence PKS. What I don't yet know is how to check that the conversion is anywhere near sane.

STmicroelectronic 65nm, 65nm SOI and 45nm Design Kit NDA's Signed

Never underestimate the time it takes to sign a legal commitment! Finally I found the right person who was able to sign for the University binding us to not revealing secrets and accepting liabilities such that I can now receive the STMicroelectronic Design Kits (Cadence calls them PDK's) from CMP for their 65nm, 65nm SOI and 45nm CMOS processes.

Now to develop several flows including various verification strategies and frontends (Synopsys' Designware, Cadence IC, PrimeTime, etc).

DATE09 TPC Meeting on Wednesday, November the 5th

The DATE09 (Design, Automation and Test in Europe) TPC (Technical Program Committee) meeting is going to be held at the awesome IET building, Savoy Place, London this year. Wednesday the 5th of November to be precise. For full details refer to the DATE09 TPC website, http://date09-tpc.ecs.soton.ac.uk/.

Update to AHB Slave Shenanigans and Massive Modelsim Migranes

AHB Slave Shenanigans: The HREADY signal is supposed to be an input from all the other AHB slaves such that they all can note that a slave is hanging the master.

Massive Modelsim Migranes: After a lot of messing about I found out the following solution (for 64 bit linux on amd64 and intel amd64 ext systems):

libhm = $MODEL_TECH/../linux_x86_64/libhm.sl

instead of the libhm.sl line in step 4 of this article from Xilinx. This applies to Modelsim SE 6.3f and the Rocket IO (or Rocket I/O?) module called MGT internally and the SmartModel SWIFT models included in Xilinx ISE9.2i.

UK DVB Channel Numbers for MythDora 5

Mythtv, for those who don't know, is a very powerful, flexible, PVR tweakers paradise which can be run on top of an existing linux OS or from one of the customised distributions available. The new version of Mythdora, 5, has a really irritating problem: using UK freeview DVB-T it doesn't assign channel numbers as you would expect. So to the rescue is a small mysql script to do just that. The channel numbers come from the awesome DigitalSpy website, one of the best collections of information on transmitted media I have ever come across.


Script:

USE mythconverg;
UPDATE channel SET channum=1 WHERE name='BBC ONE';       
UPDATE channel SET channum=2 WHERE name='BBC TWO';      
UPDATE channel SET channum=3 WHERE name='ITV1';         
UPDATE channel SET channum=4 WHERE name='Channel 4';    
UPDATE channel SET channum=5 WHERE name='Five';         
UPDATE channel SET channum=6 WHERE name='ITV2';         
UPDATE channel SET channum=7 WHERE name='BBC THREE';    
UPDATE channel SET channum=9 WHERE name='BBC FOUR';     
UPDATE channel SET channum=10 WHERE name='ITV3';         
UPDATE channel SET channum=11 WHERE name='SKY THREE';    
UPDATE channel SET channum=12 WHERE name='UKTV History'; 
UPDATE channel SET channum=13 WHERE name='Channel 4+1';  
UPDATE channel SET channum=14 WHERE name='More 4';       
UPDATE channel SET channum=16 WHERE name='QVC';          
UPDATE channel SET channum=18 WHERE name='The HITS';     
UPDATE channel SET channum=19 WHERE name='Dave';         
UPDATE channel SET channum=20 WHERE name='Virgin1';      
UPDATE channel SET channum=21 WHERE name='TMF';          
UPDATE channel SET channum=22 WHERE name='Ideal World';  
UPDATE channel SET channum=23 WHERE name='bid tv';       
UPDATE channel SET channum=24 WHERE name='price-drop tv';
UPDATE channel SET channum=28 WHERE name='ITV4';         
UPDATE channel SET channum=29 WHERE name='E4';           
UPDATE channel SET channum=30 WHERE name='E4+1';         
UPDATE channel SET channum=31 WHERE name='ITV2 +1';      
UPDATE channel SET channum=32 WHERE name='Film4';        
UPDATE channel SET channum=34 WHERE name='SETANTA SPORTS';
UPDATE channel SET channum=35 WHERE name='Five US';      
UPDATE channel SET channum=36 WHERE name='FIVER';        
UPDATE channel SET channum=37 WHERE name='smileTV';      
UPDATE channel SET channum=42 WHERE name='Nuts TV';      
UPDATE channel SET channum=43 WHERE name='Gems TV';      
UPDATE channel SET channum=44 WHERE name='GEMSTV1';      
UPDATE channel SET channum=45 WHERE name='Lottery Xtra'; 
UPDATE channel SET channum=61 WHERE name='TVX / REDHOT'; 
UPDATE channel SET channum=70 WHERE name='CBBC Channel';
UPDATE channel SET channum=71 WHERE name='CBeebies';     
UPDATE channel SET channum=75 WHERE name='CITV';         
UPDATE channel SET channum=80 WHERE name='BBC NEWS';
UPDATE channel SET channum=81 WHERE name='BBC Parliament';
UPDATE channel SET channum=82 WHERE name='Sky News';     
UPDATE channel SET channum=83 WHERE name='Sky Spts News';
UPDATE channel SET channum=87 WHERE name='Community';    
UPDATE channel SET channum=88 WHERE name='Teachers TV';  
UPDATE channel SET channum=100 WHERE name='Teletext';     
UPDATE channel SET channum=101 WHERE name='Ttext Holidays';
UPDATE channel SET channum=102 WHERE name='Rabbit';       
UPDATE channel SET channum=103 WHERE name='TeletextCasino';
UPDATE channel SET channum=104 WHERE name='Teletext on 4';
UPDATE channel SET channum=105 WHERE name='BBCi';
UPDATE channel SET channum=108 WHERE name='Sky Text';     
UPDATE channel SET channum=300 WHERE name='4TVinteractive';
UPDATE channel SET channum=301 WHERE name='301';          
UPDATE channel SET channum=302 WHERE name='302';          
UPDATE channel SET channum=303 WHERE name='303';          
UPDATE channel SET channum=304 WHERE name='tvtv DIGITAL'; 
UPDATE channel SET channum=305 WHERE name='305';          
UPDATE channel SET channum=700 WHERE name='BBC Radio 1';  
UPDATE channel SET channum=701 WHERE name='1Xtra BBC';    
UPDATE channel SET channum=702 WHERE name='BBC Radio 2';  
UPDATE channel SET channum=703 WHERE name='BBC Radio 3';  
UPDATE channel SET channum=704 WHERE name='BBC Radio 4';  
UPDATE channel SET channum=705 WHERE name='BBC R5 Live';  
UPDATE channel SET channum=706 WHERE name='BBC 5L SportsX';
UPDATE channel SET channum=707 WHERE name='BBC 6 Music';  
UPDATE channel SET channum=708 WHERE name='BBC 7';        
UPDATE channel SET channum=709 WHERE name='BBC Asian Net.';
UPDATE channel SET channum=710 WHERE name='BBC World Sv.';
UPDATE channel SET channum=711 WHERE name='The Hits Radio';
UPDATE channel SET channum=712 WHERE name='Smash Hits\!';  
UPDATE channel SET channum=713 WHERE name='Kiss';         
UPDATE channel SET channum=714 WHERE name='heat';         
UPDATE channel SET channum=715 WHERE name='Magic';        
UPDATE channel SET channum=716 WHERE name='Q';            
UPDATE channel SET channum=718 WHERE name='SMOOTH RADIO'; 
UPDATE channel SET channum=721 WHERE name='MOJO';         
UPDATE channel SET channum=722 WHERE name='Kerrang\!';     
UPDATE channel SET channum=723 WHERE name='talkSPORT';    
UPDATE channel SET channum=724 WHERE name='Clyde 1';      
UPDATE channel SET channum=725 WHERE name='Premier Radio';
UPDATE channel SET channum=727 WHERE name='Virgin Radio'; 
UPDATE channel SET channum=728 WHERE name='Heart';        

To use it cut and paste the SQL into a text file called channel_num_fix.sql. Then run as root:

/etc/init.d/mythbackend stop
mysql -u mythtv -p < channel_num_fix.sql
/etc/init.d/mythbackend start

2 Potential warnings here: Firstly I get you to stop the backend. I am uncertain that is necessary, however on your own head be it. Also if you have channels not listed I would ensure they are not assigned to a channel number that one of the above channel's want. I don't know what would happen, perhaps nothing bad as each channel has a unique ID as well as its number.

AHB Slave Shenanigans and Massive Modelsim Migranes

Setting up and running an ARM AMBA bus is not too tricky, and it is quite a neat standard. However in this case my student seems to have copied a rather cunning implementation from Gaisler Research's GRLIB. However the AMBA standard document seems to be rather inconsistent one one point: The HREADY signal is defined to be an input and an output for all AHB slaves, but for the life of me I can't find another mention of it, nor does it seem sensible. I shall consult Prof Flynn who is working here, as he developed AMBA and has worked with it for many years. If you are thinking of making your own GPL'ed AHB slave look no further than the Gaisler Research ahbram.vhd.

Modelsim and smartmodels (specifically the Rocket IO, MGT smartmodel). Good grief, this is a non-trivial procedure. Compile the models, install the models then make lots of opaque changes to the modelsim.ini file and it still doesn't work! Don't know why yet, but will post when I do.

I'm getting a Virtex-5 ML505

Which, to me is great news. Up till now I have been using the excellent Xilinx XUP board however it has one real failing: the ports labelled SATA on the XUP are not capable of talking to SATA devices. They don't support Out Of Band signalling.

The Virtex-5 LXT based ML505 however does support the full SATA specification, as well as a lot of others besides. The reason is more advanced Rocket IO ports.

Back from holiday....

Spent a lovely week with my wife and other close family in the south west of England, all the way down to the Lizard Peninsula.

I get to attend the IDESA "Advanced Digital Physical Implementation flow" Course

IDESA is intended to kickstart the production of both analog and digital <=90nm CMOS among academia. I have got a place on the Advanced Digital Physical Implementation flow course hosted by Rutherford Appleton Laboratories in Didcot, Oxfordshire (the courses are available from other host institutions as well). The week looks very interesting:

• Day 1: Intro, design environment and toolchain + LAB
• Day 2: Leakage aware design and prevention, floorplanning LAB, design planning and libraries (including IP, soft and hard).
• Day 3: Low power flow including positioning to minimise dynamic and leakage power, physical synthesis placement and optimisation. Multiple Clock Tree Synthesis.
• Day 4: Physical Synthesis, Design for Test, Multimode and Multicorner, Routing to GDSII and labs.
• Day 5: IR drop analysys, dynamic power analysis, on chip validation and statistical static timing analysis. Lab on signoff, signoff and design finishing and layout verification. Tape-out.

Anyway I am keen to angle my way onto other courses of this quality that are on offer.

Need a SPARC version of "ARM System-on-chip Architecture"

"ARM System-on-chip Architecture", by Steve Furber is an excellent book for anyone wanting to get an OS or other software running well on the ARM range of microprocessor cores. Now if there is an equivalent for SPARC architectures please let me know as that is the current problem I am facing!

Coursework for Academics....

We are now discussing the changes to the courses for next academic year. The main push on at the moment is directed at enhancing our teaching of software to the electronics undergraduates.

COMP1010 Big changes here to alter how we teach this module. The previous course centered on teaching as much C as possible using Visual Studio, with a lab a week reinforcing the lecture topic. To improve things by engaging the students more we are moving a lot of the C syntax and content into the semester 2 course. This leaves room for the introduction of AVR microcontrollers along with a bit of computer architecture. Hopefully this will engage the students immediately. The programming will be done in AVRStudio with WinAVR as the compiler. The assessment will be significantly changed to favour two "Exam Labs" which will be open book individual assessments. The first will have a lot of direction and the second will be solving a problem. Appropriate assessment of any course is essential for its success, and I personally belive in problem based learning as one of the most enjoyable and effective techniques.

ELEC1013 The main change here is the labs have been shortened and there will be more of them. There is also an open question whether to include an AVR Microcontroller that can be used over USB or networked to encourage the Computer Science students who take this course to mess about with gadgets.

Do the multipathing first, and the mirroring afterwards!

If you are using a mirrored root under Disksuite and wish to enable mpxio I wish you well. It is a devil of a job, mainly due to the fact that stmsboot won't recognise your metadevice as a STMS device and so won't enable it.

So to fix it here is the answer:

1. Back everything up. EVERYTHING
2. Follow the guide here to undo the mirrored root
3. Run stmsboot -e and reboot immediately
4. Everything should now be correctly multipathed using mpxio
5. Rebuild all the mirrored root and other devices

and next time, do the multipathing first and the mirroring afterwards!

Adding a package called "leon-bootloader" to Angstrom

I wonder how to handle this. Typically Angstrom downloads source packages from the internet as needed, however in this case the bootloader is never supplied as a separate download. Downloading and extracting snapgear linux to get at it doesn't appeal, neither does distributing it by myself. I am also uncertain whether Angstrom would accept a complete source package in their download system for such a niche market.

Imagination Technologies Visit

I have just had the pleasure of hosting some representatives of Imagination Technologies.

It was a productive day, and I am looking forward to some really interesting projects and cooperation coming our way.

Writing Referral Exam Questions

Unfortunately not all students pass the exam, and this is their second chance. History suggests that some will work very hard and do well, and some will (despite hard work in some cases) not. In many ways this is quite a difficult part of being an academic - assessment.

The LEON3 sparc linux bootloader generation process is awful

1. Uses a combination of make and perl scripts reading from a global config.
2. Includes including includes including includes.
   
3. Variables drawn directly from .config files and the aforementioned headers, some of which are written by perl scripts driven from variables as above.
   
4. Uses gcc to edit a text file and then calls the result a .o (it is plain ASCII) after hardcoding all of the paths.

I either choose to sanitise this system, or just package it and gingerly push options in its general direction. It is also unclear what license it is under, however as it is part of a linux distro build process I believe that puts it under the GPL whether it is explicit or not.

Broken DDR DIMM replaced, now to continue..

Replaced the broken DDR DIMM (which has a lifetimes warranty) and now to get on with things.

Trouble! Things that were working just fine, now are not

Basically the system now claims it cannot see the DDR! Which is a blow. I don't know why but I am getting the dreaded 'stack pointer not set' errors and the system doesn't seem to think it has any memory. I am wondering if I need to add in a bit more manual deskewing or whether I have actually broken something (I certainly hope not!).

More to follow....

Booted the Kernel built by Angstrom on LEON3

... but not the ramdisk. I seem to be having trouble with it at the moment. I shall investigate it properly tomorrow. Perhaps I haven't got enough RAM enabled, which can be a real problem apparently. Kernel hangs if you run out without error messages.

Just to be clear: I took the kernel from snapgear linux. I just created a single large patch against vanilla 2.6.21.1. The patch is quite large and I didn't want to care about such things.

However the version of glibc and the compiler are completely different. I don't yet know if this is going to cause stability problems, but I can just constrain Angstrom to use the right versions from the snapgear toolchain. Such is the power of OpenEmbedded.

Angstrom building for SPARC

By poaching files and diffs from snapgear, Angstrom is merrily building away.

Slowly debugging issues and learning more than I ever wanted to know about the linux boot process.
Issues:

• Does it work? Angstrom at the moment is building with gcc4 not 3.
• Are there necessary glibc patches? If so I haven't done anything to apply any.
• I need to fix the ramdisk builds.
• Will udev work?

Anyway, off home now!

Beginning work on modifying angstrom...

Seems that point 1 from below is already taken care of! Angstrom is setup for a sun4cdm with a supersparc CPU. I am building it now and hope to take care of packaging it for use in TSIM and GRMON as an image etc. (not that I have TSIM unfortunately).

Snapgear Linux or Angstrom..

I am currently building and deploying Snapgear linux onto a LEON3 system aboard a xilinx-xup board. However I have several issues with Snapgear:

1. Despite all the hard work that has gone into it, it feels poorly constructed. I think they are discovering just how hard it is to maintain and build embedded linux distros. I am thinking of the early days of OpenZaurus
   
2. Functionality that just doesn't work out of the box: dhclient, openssl, ssh and sshd. Pretty fundamental tools here. Not to complain about the good work of uCdot

I think I shall try to get Ångström up and running as it is much better at handling these things. The main effort will be:

1. Toolchain. Assembling the patches and CFLAGS etc for the toolchain (glibc in the first instance).
2. Backend: Packaging the system such that it will be able to build images for the various GR tools.

Further posts will follow as I address these issues. Overall I think it is more valuable than fixing problems in Snapgear.

A brand new XUP board is sitting on my desk...

... and even better it doesn't have the old jtag programmer onboard so it works with GRMON! So much better than the serial debug system I was using before. It programs about 10 times faster for a start.

Where to go from here: System C + Hardware/Software Codesign?

The GRLIB components and tools by being GPL'ed and available in VHDL form are a serious attraction for Hardware/Software Codesign.

It isn't quite clear yet how usable/possible this will be, but it would allow us access to real, selectable hardware examples. Quite a proposition.

MSc Projects offered...

I have offered the following MSc projects:

1. Remove the LEON3 core and substitute an OpenSPARC (possibly the single core, wishbone compatible variant).
2. Build a SATA controller
3. Explore the LEON3 GRLIB design space on ASIC and FPGA (i.e. how fast, how big, etc)
4. Build an AHB parallel port (high speed, of course. Maybe a bit of a ram buffer?)
5. Enable the Xilinx-XUP board's CF card to program the FPGA, install a boot loader and boot linux.

They are all different vairants of tricky, with 5 probably a real problem in disguise. I think it would be best for the boot loader to be part of the FPGA (i.e. a 1k ROM or similar) to boot off the CF card.

Linux successfully executed!

Here is the first console dump of my executing linux session (the image.dsu was borrowed from the theora project). I shall have to consider that a success. Now onto the stickier proposition of how to boot and execute from a flash card using the xilinx-xup board. I am thinking of using systemACE to package the kernel and bitfile, and then targetting a linux partition on the CF card. It all depends if system ACE can actually put things into RAM, but I believe it can look like FLASH to the FPGA so all should be alright.

M:\GRMON\win32>grmon-eval.exe -uart //./com8 -ibaud 250000 -u -nb

GRMON LEON debug monitor v1.1.29 (evaluation version)

Copyright (C) 2004,2005 Gaisler Research - all rights reserved.
For latest updates, go to http://www.gaisler.com/
Comments or bug-reports to support@gaisler.com

This evaluation version will expire on 15/10/2008
try open device //./com8
###opened device //./com8

GRLIB build version: 2950

initialising ..............
detected frequency: 80 MHz

Component Vendor
LEON3 SPARC V8 Processor Gaisler Research
AHB Debug UART Gaisler Research
AHB Debug JTAG TAP Gaisler Research
GR Ethernet MAC Gaisler Research
AHB ROM Gaisler Research
AHB/APB Bridge Gaisler Research
LEON3 Debug Support Unit Gaisler Research
DDR266 Controller Gaisler Research
Generic APB UART Gaisler Research
Multi-processor Interrupt Ctrl Gaisler Research
Modular Timer Unit Gaisler Research
Keyboard PS/2 interface Gaisler Research
Text-based VGA controller Gaisler Research
Keyboard PS/2 interface Gaisler Research

Use command 'info sys' to print a detailed report of attached cores

grlib> load M:\Downloads\image.dsu
section: .stage2 at 0x40000000, size 10180 bytes
section: .vmlinux at 0x40004000, size 1232960 bytes
section: .rdimage at 0x40148f94, size 1598828 bytes
total size: 2841968 bytes (88.3 kbit/s)
read 3706 symbols
entry point: 0x40000000
grlib> run
Booting Linux
Booting Linux...
PROMLIB: Sun Boot Prom Version 0 Revision 0
Linux version 2.6.21.1 (root@brazilip-tec) (gcc version 3.2.2) #16 Mon Aug 20 19
:32:42 BRT 2007
ARCH: LEON
Vendors Slaves
Ahb masters:
0( 1: 3| 0): VENDOR_GAISLER GAISLER_LEON3
1( 1: 7| 0): VENDOR_GAISLER GAISLER_AHBUART
2( 1: 1c| 0): VENDOR_GAISLER GAISLER_AHBJTAG
3( 1: 1d| 0): VENDOR_GAISLER GAISLER_ETHMAC
Ahb slaves:
0( 1: 1b| 0): VENDOR_GAISLER Unknown device 1b
+0: 0x0 (raw:0x3fff2)
1( 1: 6| 0): VENDOR_GAISLER GAISLER_APBMST
+0: 0x80000000 (raw:0x8000fff2)
2( 1: 4| 0): VENDOR_GAISLER GAISLER_LEON3DSU
+0: 0x90000000 (raw:0x9000f002)
3( 1: 25| 0): VENDOR_GAISLER Unknown device 25
+0: 0x40000000 (raw:0x4003c002)
+1: 0xfff00100 (raw:0x10fff3)
Apb slaves:
0( 1: c| 2): VENDOR_GAISLER GAISLER_APBUART
+ 0: 0x80000100 (raw:0x10fff1)
1( 1: d| 0): VENDOR_GAISLER GAISLER_IRQMP
+ 0: 0x80000200 (raw:0x20fff1)
2( 1: 11| 8): VENDOR_GAISLER GAISLER_GPTIMER
+ 0: 0x80000300 (raw:0x30fff1)
3( 1: 7| 0): VENDOR_GAISLER GAISLER_AHBUART
+ 0: 0x80000400 (raw:0x40fff1)
4( 1: 60| 5): VENDOR_GAISLER GAISLER_KBD
+ 0: 0x80000500 (raw:0x50fff1)
5( 1: 61| 0): VENDOR_GAISLER GAISLER_VGA
+ 0: 0x80000600 (raw:0x60fff1)
6( 1: 60| 4): VENDOR_GAISLER GAISLER_KBD
+ 0: 0x80000700 (raw:0x70fff1)
7( 1: 1d|12): VENDOR_GAISLER GAISLER_ETHMAC
+ 0: 0x80000b00 (raw:0xb0fff1)
TYPE: Leon2/3 System-on-a-Chip
Ethernet address: 0:0:0:0:0:0
CACHE: direct mapped cache, set size 8k
Boot time fixup v1.6. 4/Mar/98 Jakub Jelinek (jj@ultra.linux.cz). Patching kerne
l for srmmu[Leon2]/iommu
64MB HIGHMEM available.
node 2: /cpu00 (type:cpu) (props:.node device_type mid mmu-nctx clock-frequency
uart1_baud uart2_baud )
PROM: Built device tree from rootnode 1 with 918 bytes of memory.
DEBUG: psr.impl = 0xf fsr.vers = 0x7
Built 1 zonelists. Total pages: 64302
Kernel command line: console=ttyS0,38400 init=/sbin/init
PID hash table entries: 1024 (order: 10, 4096 bytes)
Todo: init master_l10_counter
Attaching grlib apbuart serial drivers (clk:80hz):
Console: colour dummy device 80x25
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
Memory: 252736k/262144k available (968k kernel code, 9244k reserved, 112k data,
116k init, 65536k highmem)
Mount-cache hash table entries: 512
checking if image is initramfs...it isn't (no cpio magic); looks like an initrd
Freeing initrd memory: 1561k freed
highmem bounce pool size: 64 pages
io scheduler noop registered
io scheduler cfq registered (default)
grlib apbuart: 1 serial driver(s) at [0x80000100(irq 2)]
grlib apbuart: system frequency: 80000 khz, baud rates: 38400 38400
ttyS0 at MMIO 0x80000100 (irq = 2) is a Leon
Loading theora ...
LEON THEORA driver by Andre Costa (2007) - andre.lnc@gmail.com
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
loop: loaded (max 8 devices)
RAMDISK: Compressed image found at block 0
VFS: Mounted root (romfs filesystem) readonly.
Freeing unused kernel memory: 116k freed
init started: BusyBox v0.60.5 (2007.08.04-05:15+0000) multi-call binary
Shell invoked to run file: /etc/init.d/rcS
Command: #!/bin/sh
Command: mount
Please press Enter to activate this console.
Interrupt!
stopped at 0xf00140d0
grlib>

Just benchmarked my first LEON3

29.8 Dhrystones MIPS! This is an 80MHz LEON3 system with no FPU. Onwards, to linux!

Just connected to my first LEON3 SoC

... via the JTAG debugger but I am still unable to drive the DDR due to the lack of DCM modules in this particular Xilinx. I am now turning my attention to the XUP board from Digilent as they are quite common around here.

Hopefully I shall get further down that road towards the goal of booting linux on the system....

Trouble with the ML403...

Heh, should have realised it wouldn't be that easy...

Basically the ML403 differs from the ML401 & 2 by the fact that they both their Virtex-4's have 8 DCMs as opposed the 403's 4, and the LEON3 core with a DDR controller (necessary for the built in DDR memory) needs 5. It took a surprisingly long time for me to realise that's what the error message meant. Still today has been quite productive with a lot of lessons learnt.

Another lesson is that Xilinx ISE on windows will rebuild a Xilinx ISE on linux project, meaning the 20 minutes I took building and routing the first design came to nothing, as the windows machine proceeded to take about 60 minutes to perform the same task.

Linux Tomorrow

I am borrowing a Xilinx ML403 board over breakfast (in exchange for some copper pipe) so I should be testing Linux on LEON3 tomorrow. I have also provided my MSc students a tutorial getting them off the ground in messing with GRLIB which I really need to write up in our knowledgebase.

grlib is proving quick to get off the ground, I just hope it proves easy to customize too.

GRLIB now compiling in ModelSim

After some silliness with the configuration stages GRLIB is now up and running.

First thing to do is informal validation tests against the various FPGA compilation tools we have available to see what produces working code, smallest/fastest etc.

Secondly I need to download Snapgear's linux for LEON3 and examine it for correctness / niceness. I might even port the patches into Angstrom and use that as a base depending on what I find.

Final block of marking done....

Phew, glad that is over. Just got to set my MSc's going on their dissertations and help my Part III students get into and motivated over their projects.

I have given this lot of students as much feedback as I can, in an effort to improve things. A mark without comments is pretty pointless.

Platform express flow problems..

Interesting, we can get hold of Mentor's Platform Express from mentor, but not the seamless cve product that we need to simulate cores. That being said, GRLIB is looking like the only option at the moment.

Pity, however we may be able to extract a processor that we can trivially wrap for the Synopsys tool. ARMs have to be hardwired into IRQs and their bus selects however, which GRLIB seems to approach differently.

GRLIB on its own will probably be the best way, which is a pity as I think the Synopsys tools are great. Without a core and a bunch of licenses however we are not going to get very far.

Wanted: Alternatives to Design Compiler

There are only two synopsys licenses, which is far too few to teach with. I shall talk to Synopsys to see if I can get some more from them for teaching purposes.

As we have lots of Mentor licenses I shall investigate their products more.

LEON3 as a core until we get an ARM

The SPARC v8 LEON3 and the associated GRLIB should fit in the planned teaching I have in mind:

http://www.gaisler.com/cms/index.php?option=com_content&task=view&id=13&Itemid=53

It is what we needed: A core! It is also GPL licensed so we are legally entitled to and might be able to crack it open to better teach cache controllers and DMA controllers.

esdsun4 now running

We are still using two old solaris workhorses: esdsun3 and esdsun4. Both are Enterprise 3500's with 6x 400MHz USII with 8MB of cache and a bunch of FCAL HDDs. Just got the second one working. What it troubling is that they are not much slower (if at all) than the V210's we have. Contrasting enterprise kit (old) with new budget kit doesn't reveal that many differences.

I am now Master of Masters!

Not as cool as it sounds, but I hope to do a good job. I now organize and manage the MSc summer projects.

Success targetting coreAssembler on FPGA

Just instantiated an AMBA bus structure into a cyclone III FPGA from Altera. Toolchain was a bit of a pain but most of that now sorted out. Now in a position to make arbitrary bus and peripheral structures. Just need cores now. And some form of memory.

coreAssembler -> Designware Compiler -> Quartus II

What a productive night.

Designware Compiler being difficult...

Trying to use Designware compiler to build for altera FPGAs.

Quartus II supplies the needed db files, however it doesn't seem to be consistent! I can't make any small designs, but I have successfully built a large AMBA structure for a cyclone II. Trouble is the libraries are rated as compatible with designware compiler 2004, not 2007.

The compiler dies with an internal error and a stack-dump. Will try driving design compiler by hand first to get more design information.

Sun saga continues

Tried my cunning plan. Completely failed to work.

New plan:

Install Sol9 and StorageTek SAN from scratch: a
Now all I have to do is:

1. change vfstab
2. change boot in eeprom
3. boot to new disks
4. move fiber
5. setup mirrored root
6. .....
   
7. profit!!!!
   

Servicing Suns

I am trying to boot one of our cad servers from half of a mirror pulled from the other half. Predicatably it is being difficult, however if I want to preserve the exact setup I am at a loss how else to do it.

Still I think I am a sucker for punishment. Installing from scratch may, eventually, be the way to go from here.

The first batch of real exam marking this year

I have several thoughts for essential exam marking equipment:

1. A stamp with a large red `?'
2. Calming tablets

You need 1 when a student does a brain dump or creates an unconnected string of words. You need 2 when your paranoia increases as a student returns an answer that matches your perfect one. Luckily either extreme is rare, however they typically dominate the whole script.

First Post!

Heh, be warned, the humour of the above post is what you are likely to encounter here....