The next SoC design - working title "Transmute" begins

I have a fun new hobby - designing the digital part of a new, mixed signal SoC which we are building here. It is my intention to blog the full design flow discussing the various challenges and issues as we encounter them.

Design Basics

• Foundry
• Technology
• IP
• Flow
  

The importance of these choices of these depends on the following thoughts:

• What have we done before
• Who have we worked with before
• What have we got that works
• What we need to do and what we would like to do
  

Planning a chip begins after you decide the basics above, i.e. foundry, technology and the needed parts and finally tool support. Sometimes in industry you have the luxury of a couple of other choices e.g.:

• Cell library (we use the ST supplied one but there are others, Faraday for example)

Basic Overview Spec

1. Two full custom ADCs for testing and evaluation
2. A single core SoC to test our mixed signal integration and apply tests
   
3. Simple connectivity to the SoC

Initial Decisions

In our case after some mulling over our experiences we decided on:

1. ST Microelectronics via the Circuits Multi-Projets MPW broker
2. Their HCMOS9 130nm process
3. IP Blocks (see below)
   
4. The flow, more on that later

 IP Blocks

As a university our access to IP is somewhat limited. Making a SoC requires quite a few modules like memory controllers etc.

However to the rescue rides Synopsys' DesignWare Library. It includes a basic selection of AMBA AHB/APB bus connected peripheral set and a memory controller which supports SDRAM and Flash.

To drive the the DesignWare library is the coreTools GUI (which is surprisingly hard to find) which in a nice graphical environment enables you to construct AMBA bus structures containing DesignWare peripherals. So this drives our choice of some of the tools (coreTools and DesignCompiler Ultra) as well as their DesignWare basic IP.

Onto a much more interesting question. What core to use? Considering our other IP is AMBA an ARM is the most likely choice however there are others we might use:

• The LEON3 from Aeroflex is a Opensource (GPL), VHDL 32 bit SPARCv8 CPU with an AMBA bus. It is, however, very much bound to its peripheral library and autoconfiguration so would take a lot of work. It would also need to be customised to use the HCMOS9 SRAM blocks
• The IBM PPC 405 is a 32 bit PowerPC core designed for embedding which is licensed to universities for teaching and education. It is the distribution created for the Synopsys flow which allows easy integration with AMBA peripherals. It is a softcore, i.e. it would need to be synthesised from RTL

In this case we wish to reduce our risk and design effort. Licensable from CMP is a foundry guaranteed ARM946E-S hard IP (i.e. they have already synthesized it and checked it) on their 130nm process. So we are going ahead with DesignWare soft IP surrounding a hard IP ARM946E-S. The benefits of hard IP are that ST have de-risked the design for us.

The features of the ARM946E-S are:

• Excellent compiler/OS/application support. ARM is one of the best supported architectures in both Opensource and commercial software
• Small and quick, approximately 3mm² and clocking at 200MHz (both of these are significantly derated estimates at this stage of the design
• MMU allowing full OS support
  

In addition we need the following types of IP:

• A PLL - this is pretty much required for any SoC these days (available from CMP)
• Level shifters and isolators - needed to try advanced power saving strategies in digital logic

The current initial design of the digital segment of our chip is best shown in a block diagram below:

We will talk of flows and the analogue integration later.....