Tuesday, September 2, 2008

Cadence rc LEON3 compilation success

I have just used Cadence SoC's rc (RTL Compiler) to build a verilog netlist of a LEON3 SoC. The estimates are that it would run at 300MHz on a 120nm process.

Now I just need to progress getting it into encounter to start floorplanning. And a large amount of verification and checking that it is valid and correct.
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1 comment:

  1. UnknownApril 17, 2009 at 11:17 AM

    Hi,
    I am Brazilian Master Student at UFRGS. I tried to synthetize the LEON 3 Processor using RTL Compiler(Cadence), but i did not obtain success.
    Would I like knowledge if you have some tip about to synthetize the LEON 3 using RTL Compiler ?

    Thanks,
    Daniel Guimarães Jr.

    ReplyDelete