Router Resurrection....

Just fixed a Linksys BEFSR41 v2. Seems that the power brick had a standard cylinder DC plug however the central bore was about 1mm larger than the socket's central pin. I originally thought that I just had a 3rd party powerbrick, however a colleague of mine recognised the router and explained that it was a similar problem for him. Maybe a dodgy batch? Anyway the DC socket was a standard part, the warranty was void through age anyway so a cheap replacement, £1.11, has fixed the problem.

Better than new.

Firefox disrespecting your download preferences on MacOSX?

On OSX (Apple Macintosh Leopard, 10.5) does firefox ignore your download directory and constantly dump files on the desktop? Does your desktop get incredibly cluttered?

In all likelihood you have updated to the version of OSX you have now. And it has left behind a piece that is ruining your day: ~/Library/Preferences/com.apple.internet.plist

Copy this to your Desktop, download something and test it out. You should suddenly find that the firefox is honoring its preference.

ESSCIRC Summary...

Sorry for the lack of daily updates. What can I say? Every day was an 8:30 start, finishing at 18:00 sometimes. This is without anyone leaving in the sessions I was in, which if you have ever been to a conference is really unusual.

An interesting combination of academic, student and company presentation. Interestingly the companies typically showed much more finished products.

Anyway it was really well worth the visit (not to mention the whiskey tasting or the visit to murrayfield....)

Cadence Encounter SEGV on start faults cured III

It is the fonts. I had similar segv crashes using X on windows without the fixed and misc fonts installed. Seems Cadence likes its traditional X client setup. Now I just need to diagnose what font packages I haven't installed / installed in the wrong places.

Day 1 Done

I particularly liked the plenary Technology Interfacing for Fabless Semiconductor Companies by
Vahid Manian. For those who don't know he works for Broadcom. It was really interesting hearing how they manage their relationships with the CMOS foundries and how much effort they put into owning their own cell libraries and techniques.

More to follow....

Catch up with me at ESSCIRC next week

ESSCIRC 2008, Edinburgh. I am really looking forward to this conference, and I am meeting up with Cadence and NMI to discuss the Cadence Academic Network. Should be good.

Look out for me with a badge from Southampton University.

Are you and academic and thinking of buying a Xilinx development kit?

Then I can't plug Digilent enough. They have two very large FPGA boards available for very keen prices. The first is the Xilinx XUP, which is a XC2VP30 Virtex 2 Pro with 2 405PPC cores. This board supports DDR and is a great way to get started with prototyping Gaisler SoC designs. The excellent academic price is only $299! One word of warning: this board doesn't have true SATA ports depite there being connectors and labels saying SATA. They are high speed digital data links that are SATA like but are SATA non-standard and cannot connect to a SATA HDD. No out of band signals.

The second is an uprated ML505. This is identical to the standard Xilinx ML505, but it has a much larger FPGA on it (XC5VLX110T) and comes with a JTAG programmer. The ML505 from Xilinx doesn't. Total price $750.

I have hunted about and the prices here end up hundreds of pounds less than full commercial prices. In the case of the ML505 it is about £300.

Why getting a linksys WRT54GL wireless router is a good idea...

Basically, the WRT54G router is now on the 8th revision of the hardware and has had it's software updated since it was made. For example the current software set can have its web management software secured with SSL and supports WPA/WPA2, concepts that didn't exist when they started making the model.

Also if you need to do something really special you can remove the stock firmware and replace it with OpenWRT linux, almost limitlessly configurable. One point: the linux compatible version is sold separately these days as the WRT54GL

Just P&R'ed and unconstrained SoC using Cadence Encounter

Excellent, a LEON3, DDR controller, misc peripherals using a ST Microelectronics 120nm process from CMP. It was badly done, unconstrained and in all likelihood completely non-functional but it is a real start.
Taking it forward:

1. Verifying the rc generated verilog netlist is functionally correct. Modelsim will work for us here.
2. Using rc to generate the netlist from two technology files: Low Leakage and High Speed to allow the critical path to run faster.
   
3. Generalizing the setup of Encounter such that it fully uses the whole designkit in an easy-to-use package.
   
4. P&R'ing a whole SoC.
5. Verifying the back-extracted layout is fully correct.
   

Cadence Encounter SEGV on start faults cured II

New diagnosis: The problem occurs when it attempts to display the window on Fedora Core 8 with or without compiz. I wonder if it ever worked? New cure: SEE LATEST POST ON THIS

xorg-x11-server-Xorg-1.3.0.0-47.fc8
Linux **** 2.6.25.14-69.fc8 #1 SMP Mon Aug 4 14:00:45 EDT 2008 x86_64 x86_64 x86_64 GNU/Linux

Dump of problem:

encounter
This version requires license using cdslmd daemon.
Checking out Encounter license ...
SOC_Encounter_GXL 6.2 license checkout succeeded.
INFO: Current OA version selected: OA22
Starting console server on port esdcad4.ecs.soton.ac.uk:8888 ..
sourcing /home/esdcad/software/cadence/linux/soc62_USR4/tools/fe/etc/rdaDSL.tcl
*******************************************************************
*   Copyright (c)  Cadence Design Systems, Inc.  1996 - 2007.     *
*                     All rights reserved.                        *
*                                                                 *
*                                                                 *
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* This program contains confidential and trade secret information *
* of Cadence Design Systems, Inc. and is protected by copyright   *
* law and international treaties.  Any reproduction, use,         *
* distribution or disclosure of this program or any portion of it,*
* or any attempt to obtain a human-readable version of this       *
* program, without the express, prior written consent of          *
* Cadence Design Systems, Inc., is strictly prohibited.           *
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*******************************************************************

@(#)CDS: First Encounter v06.20-s285_1 (32bit) 03/20/2008 18:59 (Linux 2.4)
@(#)CDS: NanoRoute v06.20-s222 NR080304-1637/USR54-UB (database version 2.30, 58.1.0) {superthreading v1.10}
@(#)CDS: CeltIC v06.20-s075_1 (32bit) 03/06/2008 22:51:18 (Linux 2.4.21-37.ELsmp)
@(#)CDS: CTE v06.20-s256_1 (32bit) Mar 20 2008 15:56:31 (Linux 2.4.21-37.ELsmp)
--- Starting "First Encounter v06.20-s285_1" on Thu Sep  4 15:05:31 (mem=62.9M) ---
--- Running on esdcad4.ecs.soton.ac.uk (x86_64 w/Linux 2.6.9-78.0.1.ELsmp) ---
This version was compiled on Thu Mar 20 18:59:03 PDT 2008.
Set DBUPerIGU to 1000.
Set Default Mode Capacitance Scale Factor to 1.00
Set Detail Mode Capacitance Scale Factor to 1.00
Set Coupling Capacitance Scale Factor to 1.00
Set Resistance Scale Factor to 1.00
Set net toggle Scale Factor to 1.00
Set Shrink Factor to 1.00000
Encounter terminated by internal (SEGV) error/signal...
*** Stack trace in log file.

Cadence Encounter SEGV on start faults cured

Problem: On RHEL 4u7 encounter from soc52 and soc62 crashes with a SEGV on run. In the stacktrace are lots of Tcl type errors.

Solution: Install RHEL 3! Seriously, running the most supported OS, in this case RHEL 3, solved the problem.

Cadence rc LEON3 compilation success

I have just used Cadence SoC's rc (RTL Compiler) to build a verilog netlist of a LEON3 SoC. The estimates are that it would run at 300MHz on a 120nm process.

Now I just need to progress getting it into encounter to start floorplanning. And a large amount of verification and checking that it is valid and correct.