Friday, 6 November 2009

IBM PowerPC™ 405-S: Verification of the RTL with the supplied Artisan SRAMs

[Please note that these instructions reference the 1.00a version of the Synopsys PowerPC™ 405-S coreKit which is the version provided in the University IP package from IBM. There are updated versions available from Synopsys that address several of the issues outlined below. These are specifically commented on where known.]

This is the second article in the series (click here for the series index) describing the IBM PowerPC™ 405 synthesizable core and peripherals and will cover what needs to be done to take the IP and get the RTL simulating with the modern versions of the necessary Synopsys Tools and a simulator of your choice.

Initial Unpacking
When you first unpack the DesignWare PowerPC405-S™ implementation view coreKit (the archive is called DW_ppc405-FS_iv_1.0a_AV.tar.gz) it expands to a directory DW_ppc405-FS_iv_1.0a_AV.

The first thing you should do is begin reading the excellently written User Guide (docs/405_ivug.pdf) which provides the suggested flows along with the Release Note (docs/iv_rn.pdf) that specifies the tools and environment with which you need to build the processor.

However the software versions requested by the release note to simulate the RTL is problematic. I have listed below the required software in black, the lowest version available in red and the highest version available at time of writing in blue:

Required:
  1. Synopsys coreConsultant, Version V-2004.03-CT4.4.2 Z-2007.06-SP5 C-2009.06-3
  2. Synopsys Vera System Verifier, Version 6.3.0 Z-2006.12 A-2007.12-12
  3. Synopsys Design Compiler, Version U-2004.06-SP2 Z-2007.03-SP2 C-2009.06-SP2
One of:
  1. Synopsys VCS, Version 7.1 Y-2006.06-SP1 C-2009.06-1
  2. Mentor Graphics ModelSim, Version 5.7g 6.5c
  3. Cadence NC-Verilog, Version 5.1 8.1
As you can see the specified tool versions are simply not available.
[Note: at the time of publication the current commercial coreKit is version 3, not the version 1.0a discussed here and supports the current generation of tools.]

In the following sections I will describe how to get the PowerPC 405 verified with the following tool set:
  1. coreTools C-2009.06
  2. DC Ultra B-2008.09
  3. DesignWare 2009.06a
  4. vera A-2007.12
  5. NC-Verilog (Integrated Unified Simulator) 8.1
Before you proceed further be sure that all the necessary environment variables from the documentation are set and the correct executables are the in the path.

Getting Started

The educational distribution doesn't come packaged as a single coreKit file but as a compressed, already installed, coreKit directory. To get started fire up coreConsultant and select File > New Workspace. Point the installed coreKit path at the unpacked .tar.gz and choose a directory as the root and a new name for the Workspace. In the following examples we will use the workspace RTLVerification created in the same directory as the unpacked coreKit.

You should now have a directory tree in this root beginning with the name of the workspace. It is similar to the unpacked .tar.gz and populated with symlinks to some of the original files.

Choose the built in Artisan 130LVFSG RAM models and proceed to the simulation stage (I will discuss integrating custom SRAMs in a later article).

Verification by Simulation: Initial Experiences

When you have successfully moved onto the "Verify Component" stage things are not so simple. As we are going to use NC Verilog be sure to choose NC_Verilog as the simulator and ensure the relevant paths are set correctly. Leave the rest of the options at their default values.

[Note: All the issues listed here (and some more of the same) are solved with one comprehensive script and a few instructions in the section below. This section is here to detail what kind of issues you may face and how to solve them to allow you to debug your own installations should this be necessary.]

Building the Vera Objects

The design of the simulation/test environment uses Vera testbench tool to provide compiled simulation objects that surround the Verilog core and a few other Verilog modules and test vectors. We need to compile these Vera objects and we do that by opening a terminal in the Workspace directory we have created (RTLVerification). Then execute this series of commands in the terminal:

cd sim/vera/src

./build_vro


The script will generate several screens full of output with no errors (a few warnings do appear). You can check the content of the sim/vera/lib directory and see the compiled .vro objects.

Running the Simulation

When you hit "simulate" you are faced with the following error message:

For some reason several script files are not correctly linked into the RTLVerification/sim/ directory, but it is easy to fix.

Open the terminal and navigate into the sim/ directory:

cd sim/
ln -s ../../DW_ppc405-FS_iv_1.0a_AV/sim/build_pli_* ./
[Note that you must have the directories setup as discussed or change the command to where the you unpacked the original coreKit directory]

Unfortunately we are not quite out of the woods yet, as the build_pli_nc.sh has to be run by hand to build the binary link between Vera and NC_Verilog. If your environment variables are set correctly then this will complete without error leaving behind the binary file libpli.so.

[Note that you need to have a 64 bit version of Vera for a 64 bit simulator and 32 bit for 32 bit. If you are building for a 32 bit simulator and 32 bit Vera on 64 bit linux edit the pli script to add an -m32 immediately after "gcc" in the compile line and "gcc" in the link line, e.g.:

elif [ `uname` = "Linux" ]; then
     gcc -m32 -fPIC -c -I$VERA_HOME/lib/vlog -I$CDS_INST_DIR/tools/verilog/include $VERA_HOME/lib/vlog/veriuser.c
     gcc -m32 -shared -o libpli.so veriuser.o $VERA_HOME/lib/vlog/libSysSciTaskpic.a
]

Retrying the simulation in the coreConsultant GUI produces the following result almost instantly:

Now I think NC Verilog is an excellent simulator however simulating an entire core in a few seconds? No.

Delving into the scripts reveals another missing file: sim/runtest. By using the same procedure as before we can link it in:

cd sim/
ln -s ../../DW_ppc405-FS_iv_1.0a_AV/sim/runtest ./

Unfortunately this script is also not in a working condition: It depends on the perl distributed by Synopsys but it is hardcoded to try one only available within IBM. However fortunately Synopsys ships this perl with coreTools. Open the file sim/runtest in your favorite text editor and change the first few lines from:

#!/afs/raleigh/cadtools/synopsys/dc/2005.09/linux/bin/snpsperl
require 5.004;
BEGIN { @INC = ( "/afs/raleigh/cadtools/synopsys/dc/2005.09/linux/lib" ); }

to:

#!$YOUR_PATH_TO_CORETOOLS/linux/dware/bin/snpsperl

require 5.004;

BEGIN { @INC = ( "$YOUR_PATH_TO_CORETOOLS/linux/dware/lib" ); }

replacing "$YOUR_PATH_TO_CORETOOLS" with the absolute path in your installation.

Trying to simulate again produces the "instant success" we will come to know and love.

Another missing file that needs to be linked into our workspace is the Makefile used to run these simulations:

cd sim/
ln -s ../../DW_ppc405-FS_iv_1.0a_AV/sim/Makefile ./

Unfortunately this Makefile has a similar problem with hardcoded paths that need correcting, as does Report.pl, runTB and hexFormal.pl. There are also numerous files that are not linked in. These issues arise from the coreKit being delivered in an installed from compressed into an archive rather than as a .coreKit file. To save you the effort of solving every one of these issues have a look at the next section. :

Verification by Simulation: Solved
[Ensure you have followed the instructions in "Getting Started" above. You should have installed a new workspace and have completed "Specify Configuration" and moved onto "Verify the Component"]

1) Open your favorite text editor and paste in the following script:

#!/bin/bash
#
# fix_sim_dir.sh
#
#Copyright Matthew Swabey (matthew@swabey.org).
#
#You are licensed to use this file in conjunction with the IBM PowerPC 405 coreKit and to make modifications as needed to this script as long as this copyright notice is kept.

#This script should be executed from the the new workspace directory after you have installed it with coreConsultant and progressed past specifying the SRAM technology.

UNPACKED_COREKIT_DIR=/export/fastcad/disktmp/mas/IBM_PUB2/DW_ppc405-FS_iv_1.0a_AV
SNPS_PERL_EXE=/home/esdcad/software/synopsys/linux/coreTools_B-2008.12-SP1/linux/dware/bin/snpsperl
SNPS_PERL_LIB=/home/esdcad/software/synopsys/linux/coreTools_B-2008.12-SP1/linux/dware/lib

#Build the vera objects with the version of vera installed
cd ./sim/vera/src
./build_vro
cd ../../..

#Link in the files needed to build the simulation of the PPC and run the testbenches
ln -s $UNPACKED_COREKIT_DIR/sim/build_pli_* ./sim/
ln -s $UNPACKED_COREKIT_DIR/sim/Makefile ./sim/
ln -s $UNPACKED_COREKIT_DIR/sim/runtest ./sim/
ln -s $UNPACKED_COREKIT_DIR/sim/Report.pl ./sim/
ln -s $UNPACKED_COREKIT_DIR/sim/scripts/hexFormat.pl ./sim/scripts/
ln -s $UNPACKED_COREKIT_DIR/sim/scripts/run405.config ./sim/scripts/
ln -s $UNPACKED_COREKIT_DIR/sim/scripts/runTB ./sim/scripts/
mkdir ./sim/testsuite
ln -s $UNPACKED_COREKIT_DIR/sim/testsuite/* ./sim/testsuite/
ln -s $UNPACKED_COREKIT_DIR/sim/testbench/*.v ./sim/testbench/
ln -s $UNPACKED_COREKIT_DIR/sim/testbench/*.inc ./sim/testbench/
ln -s $UNPACKED_COREKIT_DIR/src/rtl/*.v ./src/rtl/

#script files needing corrected perl paths separated by a space.
TO_BE_FIXED='./sim/Makefile /sim/runtest ./sim/scripts/hexFormat.pl ./sim/scripts/runTB ./sim/Report.pl'

function fix_perl_paths {
#Fix the afs paths for snpsperl
sed -i "s:/afs/raleigh/cadtools/synopsys/dc/2005.09/linux/bin/snpsperl:${SNPS_PERL_EXE}:g" $1
sed -i "s:/afs/raleigh/cadtools/synopsys/dc/2005.09/linux/lib:${SNPS_PERL_LIB}:g" $1
#Fix added for runTB
sed -i "s:/global/freeware/SunOS/5.8/perl-5.6.1/bin/perl:${SNPS_PERL_EXE}:g" $1

}

for file in $TO_BE_FIXED; do fix_perl_paths "$UNPACKED_COREKIT_DIR/$file"; done

#End of script

2) Edit the top three variables, UNPACKED_COREKIT_DIR, SNPS_PERL_EXE & SNPS_PERL_LIB to have the absolute paths to the appropriate executable or directory. There should be no spaces in the paths.


3) Save this file with a suitable name (e.g. fix_sim_dir.sh) in the new workspace you have created. Make the script executable using the command chmod u+x "filename". When you run it you should see an output that looks like this (but with many more Vera banners):

++---------------------------------------------------------------------++
 ||                     VERA System Verifier (TM)                       ||
 ||        Version: A-2007.12 () -- Thu Oct  8 11:35:39 2009            ||
 ||             Copyright (c) 1995-2004 by Synopsys, Inc.               ||
 ||                      All Rights Reserved                            ||
 ||                                                                     ||
 ||      For support, send email to vera-support@synopsys.com           ||
 ||                                                                     ||
 ||  This software and the associated documentation are confidential    ||
 ||  and proprietary to Synopsys Inc.  Your use or disclosure of this   ||
 ||  software is subject to the terms and conditions of a written       ||
 ||  license agreement between you, or your company, and Synopsys, Inc. ||
 ++---------------------------------------------------------------------++
Warning: async drive on skewed signal jtag_o.tdi, at 78 in ./p405s_jtag.vr
Warning: async drive on skewed signal jtag_o.tms, at 79 in ./p405s_jtag.vr
Compilation errors: 0
 ++---------------------------------------------------------------------++
 ||                     VERA System Verifier (TM)                       ||
 ||        Version: A-2007.12 () -- Thu Oct  8 11:35:39 2009            ||
 ||             Copyright (c) 1995-2004 by Synopsys, Inc.               ||
 ||                      All Rights Reserved                            ||
 ||                                                                     ||
 ||      For support, send email to vera-support@synopsys.com           ||
 ||                                                                     ||
 ||  This software and the associated documentation are confidential    ||
 ||  and proprietary to Synopsys Inc.  Your use or disclosure of this   ||
 ||  software is subject to the terms and conditions of a written       ||
 ||  license agreement between you, or your company, and Synopsys, Inc. ||
 ++---------------------------------------------------------------------++
Compilation errors: 0
 ++---------------------------------------------------------------------++
 ||                     VERA System Verifier (TM)                       ||
 ||        Version: A-2007.12 () -- Thu Oct  8 11:35:39 2009            ||
 ||             Copyright (c) 1995-2004 by Synopsys, Inc.               ||
 ||                      All Rights Reserved                            ||
 ||                                                                     ||
 ||      For support, send email to vera-support@synopsys.com           ||
 ||                                                                     ||
 ||  This software and the associated documentation are confidential    ||
 ||  and proprietary to Synopsys Inc.  Your use or disclosure of this   ||
 ||  software is subject to the terms and conditions of a written       ||
 ||  license agreement between you, or your company, and Synopsys, Inc. ||
 ++---------------------------------------------------------------------++
Compilation errors: 0
ln: `./sim/testbench//p405s_rambist_tb.v': File exists
ln: `./sim/testbench//tb_p405s_dataram_64X34_wrapper.v': File exists
ln: `./sim/testbench//tb_p405s_sram256x46_wrapper.v': File exists
ln: `./sim/testbench//tb_p405s_sram256x48_wrapper.v': File exists
ln: `./sim/testbench//tb_p405s_sram512x128_wrapper.v': File exists
ln: `./sim/testbench//tb_p405s_sram512x32_wrapper.v': File exists
ln: `./sim/testbench//tb_p405s_sram512x8_wrapper.v': File exists
ln: `./sim/testbench//tb_p405s_sramBytWr512x128_wrapper.v': File exists
ln: `./src/rtl//PPC405F5V1_soft.v': File exists

At this point the script will have built the vro objects using Vera, linked in all the missing files and corrected the paths in the scripts for you.

4) Enter the ./sim directory in the workspace and run the build_pli_nc.sh script by hand to build the binary link between Vera and NC_Verilog. If the environment variables are set correctly then this will complete without problem leaving behind the binary file libpli.so
[Note that you need to have a 64 bit version of Vera for a 64 bit simulator and 32 bit for 32 bit. If you are building for a 32 bit simulator and Vera on a 64 bit computer edit the scripts to add an -m32 immediately after "gcc" in the compile line and "gcc" in the link line:

elif [ `uname` = "Linux" ]; then
     gcc -m32 -fPIC -c -I$VERA_HOME/lib/vlog -I$CDS_INST_DIR/tools/verilog/include $VERA_HOME/lib/vlog/veriuser.c
     gcc -m32 -shared -o libpli.so veriuser.o $VERA_HOME/lib/vlog/libSysSciTaskpic.a
]

5) Return to the coreConsultant GUI, check you have selected the correct test suite, simulator and other variables and click "Apply" to be rewarded with:



This will take quite a while, so enjoy a well earned cup of tea/coffee/other until it completes:


6) Check the reports for anything interesting or anomalous

7) ...

8) Profit!

Published with permission from IBM and Synopsys

IBM PowerPC™ 405-S: Getting started

Synthesizable RTL versions of IBM's excellent embeddable PowerPC™ line of processors (the 405, 460 and the 460 FPU) are available to SoC designers from Synopsys' Star IP Program and this Star IP PowerPC™ 405-S is also available to Educators. Further embeddable PowerPC™ cores for synthesis are also available from AMCC.

In a series of articles I will show how to take the educational soft IP download, verify the 405 core and put it to work bonded to some of Synopsys' DesignWare IP.

Currently the articles in this series are:

1) Getting started with the synthesizable IBM PowerPC405™ (this article)
2) Verification of the RTL with the supplied Artisan PDK (now owned by ARM)
3) Synthesis of the RTL with the supplied Artisan PDK
4) Verification of the Gate Level Netlist


It was with great excitement that I received the educational IP by electronic transfer. As is typical with this kind of IP the full details remain secret until the licenses are signed, but with the kind permission of IBM and Synopsys let me lift the veil a little bit for you:

Here is what you get:
  1. Synopsys PowerPC™ 405-S Design View CoreKit v1.00a - This enables full, accurate simulations to be carried out to allow evaluation of the core running a software stack
  2. Synopsys PowerPC™ 405-S Implementation View CoreKit v1.00a - This bundle contains the verilog RTL of the actual core itself along with a demonstration technology library and the verification tools to enable its functionality to be fully exercised and guaranteed. This view also contains implementation scripts to build the design from RTL through synthesis, DFT, floorplanning, placement and clock tree expansion.
  3. Specifications - An essential set of manuals describing the exact operation of the core
  4. DDR2 Memory Controller - IBM's PLB DDR2 SDRAM memory controller to allow attachment of off chip SDRAM
  5. SRAM Memory Controller - This allows a number of internal SRAM (not SDRAM!) blocks to be presented as one continuous memory space on the PLB bus to a master
  6. PCIX Controller - IBM's PLB to PCIX controller
  7. PLB Crossbar Arbiter - This enables the connection of a large number of PLB masters to one or more slave busses. With this block very complex multicore/multimaster bus structures can be created within an SoC
  8. DMA Controller - a standard component allowing DMA transfers between peripherals and memory and vice versa
  9. UIC Controller - This is the Universal Interrupt Controller, an essential device for any SoC 
  10. PLB to AHB Bridge - This is bundled in with the core but is well worth noting - this allows the use of DesignWare IP blocks which are based around the AMBA bus specification
  11. Artisan PDK - For simulation purposes an Artisan 130nm LV PDK is supplied
  12. IBM RISCWatch - A JTAG debugger to allow full trace and debugging functions on the PowerPC core
As you can see it is an embarrassment of riches - a near complete set of IP enabling a basic single core to a complex multicore PowerPC™ 405 based SoC to be realized with only the basic IO IPs outstanding (e.g. no serial port or GPIO).

Again I should like to say a heartfelt thankyou to IBM and Synopsys for making this IP available to Universities to drive our research and educational programs forward. It is also available to drive commercial embedded designs forward after licensing.

Note: As it is a Synopsys Star IP this distribution is designed for a number of industry standard simulators and the Synopsys Implementation and Signoff tool suite. The package contains pure Verilog RTL so it is technically possible to use another vendor's synthesis tool but that is well outside the scope of this series of articles (as well as being a very big job).

Published with permission from IBM and Synopsys

Wednesday, 4 November 2009

How to Re-Analyze the DesignWare Building Blocks in Synopsys Design Compiler

Design Compiler, sometimes misnamed as dc_shell, includes a selection of datapath primitives called DesignWare Building Blocks (DWBB). Sometimes after a patch or new installation you may find these complaints in your logs:

Error:   Source file for 'DW01_SUB' was not analyzed by this release of the compiler; re-analyze it. (ELAB-343)
Error:   Source file for 'DW01_DEC' was not analyzed by this release of the compiler; re-analyze it. (ELAB-343)
Error:   Source file for 'DW01_INC' was not analyzed by this release of the compiler; re-analyze it. (ELAB-343)
Error:   Source file for 'DW01_ADD' was not analyzed by this release of the compiler; re-analyze it. (ELAB-343)
Error:   Source file for 'DW01_INC' was not analyzed by this release of the compiler; re-analyze it. (ELAB-343)
Error:   Source file for 'DW01_INC' was not analyzed by this release of the compiler; re-analyze it. (ELAB-343)
Error:   Source file for 'DW01_ADD' was not analyzed by this release of the compiler; re-analyze it. (ELAB-343)
Error:   Source file for 'DW01_INC' was not analyzed by this release of the compiler; re-analyze it. (ELAB-343)
Error:   Source file for 'DW01_INC' was not analyzed by this release of the compiler; re-analyze it. (ELAB-343)

They mean the compiled DWBB library is now out of date in relation to the version of Design Compiler you have. To cure them cd to $SYNOPSYS, then

cd dw/scripts/
./dw_analyze_syn.csh

and pretty soon you will have a lovely, shiny, new set of DesignWare Building Blocks!

[Note that this information also applied to VCS but use
cd dw/scripts/
./dw_analyze_sim.csh
]