Friday, 4 December 2009

IBM PowerPC™ 405-S: Synthesis of the RTL with the supplied Artisan Cell Library

[Please note that these instructions reference the 1.00a version of the Synopsys PowerPC™ 405-S coreKit which is the version provided in the University IP package from IBM. There are updated versions available from Synopsys that address several of the issues outlined below. These are specifically commented on where known.]

This is the third article in this series (click here for the series index) describing the IBM PowerPC™ 405 synthesizable core and peripherals and will cover taking the IP through RTL synthesis and scan chain insertion with the modern versions of the Synopsys tools using the supplied Artisan Library. Integrating a custom library will be addressed in a future article.

This article assumes you have used the previous articles to unpack and install the software to create a functioning simulation environment.

Getting Started: Understanding the Problem

The relevant part of the instruction manual (docs/405_ivug.pdf) is:

Chapter 6: RTL-to-Gates Synthesis

In this chapter we are going to assume that the default Core clock of 250MHz and PLB clock of 125MHz are acceptable, along with the 130nm Artisan library designed for TSMC processes.

Synthesis Scripts
Entering the dc subdirectory of the workspace shows the files in place however a little more digging and we can see that the dc/scripts directory is missing. Using an identical technique to the previous article we can create and populate it.
[Note, in a similar vein to the last article all of the changes will be summarised in a script and instructions at the end]

cd dc

mkdir scripts
cd scripts
ln -s ../../../DW_ppc405-FS_iv_1.0a_AV/dc/scripts/* ./

The script system automates the flow from RTL, Constraints and Cell Library to a gate level netlist:
  • run_compile.csh - as the "master" script it sets environment variables and then executes the desired tool, sourcing the setup.tcl script and the appropriate stage script where the stages are "elaboration", "synthesis" and "design for test"
  • scripts/p405s_elab.tcl - reads the environment variables set and executes Design Compiler to elaborate the design and save it in a .db file
  • scripts/p405s_compile.tcl - reads the environment variables set and executes Design Compiler on the elaborated design to synthesize the design and save the resulting netlist, reports and other useful outputs
  • scripts/p405s_dft.tcl - reads the environment variables set and executes Design Compiler on the synthesized design to stitch the scan chains together and enable design for test strategies
Constraints
This scripting system relies on reading design constraints held in another directory:

dc/constraints

A design without appropriate constraints is basically useless as RTL is insufficient to create a functional circuit. The constraints for this processor are complex due to the presence of 3 clock domains (core, peripheral bus and JTAG) and two test modes. The constraint files contain the following information:
  • PPC405F5V1_capture.cons - This is responsible for creating environment variables containing data on the various clock speeds and parameters. It also identifies the clock ports in the design. It also specifies some of the different clock domains.
  • PPC405F5V1_clock.cons - This file uses the variables calculated in the constraint file PPC405F5V1_capture.cons to apply constraints to the clocks in the design.
  • PPC405F5V1_compile_directives.cons - Instructs Design Compiler to fix multiple port nets, optimise a group of paths at a time for slack as opposed to one path at a time. It also enables a check on clock gating.
  • PPC405F5V1_drc.cons - This file constrains the fanouts of the nets and sets attributes on some of the clock control logic so it will pass DRC.
  • PPC405F5V1_functional.cons - Creates false paths and multicycle paths through the RAM BIST and Debug sections of the design to allow efficient synthesis.
  • PPC405F5V1_group_paths.cons – Only two constraints are added here grouping all the inputs and all the outputs together for efficient synthesis.
  • PPC405F5V1_in_out.cons – This applies driving gates to all inputs and loads to all outputs, again to improve the synthesis and increase the accuracy of the reporting Design Compiler is able to achieve. Importantly the characteristics of the clocks are further constrained in this file. Finally more false paths are assigned to the BIST structures, JTAG and test ports.
  • PPC405F5V1_shift.cons – This sets the period on the various clock lines of the design when the design is in one of its test modes.
  • PPC405F5V1_test.cons - This contains the complex constraints which drive Test Compiler when it inserts scan chains and test modes automatically. It includes defining the scan in/out ports and the state of the various pins in test mode. This presents a particular issue which will be addressed later as the syntax and capabilities of Deign Compiler have changed very significantly.
Getting Started: Planning the Solution

The first priority for us is that Design Compiler no longer supports saving the design in .db form so we need to repurpose the scripts to store the design in a more modern database. Design Compiler has also changed clock gating and operand isolation commands and compilation to accomodate modern 90nm and below CMOS. Considering that a major rebuild is necessary I am going to show you how to synthesis the design preparing for the use of Milkyway Databases and the Design Compiler Topographical feature. This will enable the porting of this design to 90nm CMOS and below in the future.

In the current system each tool is setup to use files from the Artisan library in the synthesis flow by a single Tcl script which detects what tool is running the script and then configures variables appropriately. This script is called at the start of each specific tool script. There is a lot of useful help in the current scripts as the series of improvements to Design Compiler rely on physical information from the cell library to improve its decisions. The major improvement for sub 90nm CMOS is done by the logic synthesis tool performing a quick preliminary cell placement so it can better model delay, capacitance and power costs of the design during synthesis (topographical mode).

In the following sections the updates required to each individual script are discussed.

Primary Stage Scripts

The main changes to all scripts was a change to save and load the design using the more modern .ddc database format.
[A normal Synopsys flow would store the design in the Milkyway database alongside physical data from the Cell Library but this version of the IP was not designed for this.]

Control Script: run_compile.csh

The master control script parses flags given to it on the command line and then executes Design Compiler in the tcl shell mode running the appropriate stage script. The only change to this script is:

Added a flag -topo to run Design Compiler in topological mode which will enable the use of Milkyway databases in Design Compiler.

[That being said if you are going to use the -ultra flag or the -topo flag you might want to edit the line dc_shell-t -topo -f ./scripts/p405s_compile.tcl | tee logs/p405s_compile.log to include the correct -num_cpus X where X matches the number of processors and licenses you have for faster compiles. This isn't trivial to add as an option to the .csh script without introducing a dependency on the getopts binary so I have left it undone.]

Setup: scripts/setup.tcl

The setup script is run at the start of each and every stage. It pulls in the libraries and sets up a few global variables.

The main changes needed to bring this script into line with modern tools is to include information that would normally be used by Physical Compiler in Design Compiler to support its Topological mode when the -topo mode is specified. This is necessary to manage the shift of importance away from gates (in 130nm and above) to wire lengths (in 90nm and below) which begin to dominate the performance of a design. The physical information is used to perform a rough placement allowing wireloads to be estimated much more accurately. It also has allowed the introduction of novel features such as congestion aware routing which will attempt to address routing issues at a netlist level.

This information is already in there as it was used by the static timing analyses and power estimation tools, but it needs to be enabled when the new topological flag is asserted.

Elaboration: scripts/p405s_elab.tcl

Elaboration consists of reading in HDL files and constructing a representation of the design using components from the cell libraries, i.e. parsing the source code into a generic technology (GTECH) gate-level netlist which is then saved.

The main improvements to the p405_elab.tcl scripts are:
  • Removal of obsolete commands
  • Conversion of the HDL commands from acs type to analyze types
  • Rewriting of the scan chain insertion script section to remove obsolete commands set_scan_signal with set_dft_signal and moving them into the p405s_compile.tcl script
Compilation: scripts/p405s_compile.tcl

This stage reads in the gate netlist created in the previous elaboration phase and maps it to the specific gates from the chosen cell library, applies constraints and synthesizes an actual working gate level netlist using the target technology.
  • Replacement of the -ultra flag with the compile_ultra command
  • Force the use of the compile_ultra command when in topographical mode
  • Modification of the compile command to insert the scan flops
  • Removal of nested if's by building a compile string which is evaluated
Design for Test: scripts/p405s_dft.tcl

In this phase the scan chains are built from the scan flops inserted into the design in the previous script. The design is then incrementally recompiled to minimize the scan logic and the appropriate reports and the test strategies are generated. Note that while few changes were needed to this script the scan constraints and options were completely replaced.
  • The script now preserves the use of the -high flag from synthesis to increase the effort of the incremental recompile
Constraints


There were only two constraint files that needed updating but one needed a complete rebuild to support the new syntax of Test Compiler.

constraints/PPC405F5V1_functional.cons

This file requires a slight modification to cope with a change in Design Compiler's internal bus naming style from signal[0] to signal<0>.


constraints/PPC405F5V1_test.cons

This file required a complete rebuild to manage the syntax changes in the new version of Test Compiler. The major changes are:
  • Replacement of create_test_clock, set_scan_signal, set_signal_type and set_test_hold with appropriate set_dft_signal
    declarations
  • Replacement of set_dft_optimization_configuration with set_dft_insertion_configuration
  • Reworking of set_scan_configuration flags

Synthesis: Solved

There is one script to link the needed files and one unified patch file which will update all the relevant tool scripts and constraint files to work correctly.

1) Open your favorite text editor and paste in the following script:

#!/bin/bash
#
# fix_dc_dir.sh
#
#Copyright Matthew Swabey (matthew@swabey.org).
#
#You are licensed to use this file in conjunction with the IBM PowerPC 405 coreKit and to make modifications as needed to this script as long as this copyright notice is kept.

#This script should be executed from the the new workspace after you have installed it with coreConsultant.

UNPACKED_COREKIT_DIR=/export/fastcad/disktmp/mas/IBM_PUB3/DW_ppc405-FS_iv_1.0a_AV

#Link the script files needed to synthesise the PPC405 into the workspace from the installed coreKit
cd dc
mkdir scripts
cd scripts
ln -s $UNPACKED_COREKIT_DIR/dc/scripts/* ./
cd ..

cd ..

#Apply the unified patch to update the build scripts and constraint scripts
patch -u -p0 < `dirname $0`/fix_dc.diff

2) Edit the top variable, UNPACKED_COREKIT_DIR to have the absolute path to the unpacked coreKit directory. There should be no spaces in the paths.

3) Save this file with a suitable name (e.g. fix_dc_dir.sh) in the new workspace you have created. Make the script executable using the command chmod u+x "filename".

4) Open a new blank file and paste in the following unified diff:

diff -ru ../../IBM/DW_ppc405-FS_iv_1.0a_AV/dc/constraints/PPC405F5V1_functional.cons ./dc/constraints/PPC405F5V1_functional.cons
--- ../../IBM/DW_ppc405-FS_iv_1.0a_AV/dc/constraints/PPC405F5V1_functional.cons 2005-10-17 16:31:05.000000000 +0100
+++ ./dc/constraints/PPC405F5V1_functional.cons 2009-11-09 18:18:07.608824678 +0000
@@ -3,6 +3,9 @@
 #
 #  Copyright (c) International Business Machines Corporation, 2005.
 #
+#  Modified by Dr Matthew Swabey matthew@swabey.org to support the modern
+#  synopsys design tools and techniques.
+#
 #  This file contains trade secrets and other proprietary and confidential
 #  information of International Business Machines Corporation which are
 #  protected by copyright and other intellectual property rights and shall
@@ -49,9 +52,9 @@
 #core|cpu_topSch|exe_topSch|loadSteeringSch|ocmData_NEG[*]  I _ _ * GPRWT+R
 #core|cpu_topSch|exe_topSch|gprLpIn[*]  I DC DC GPRWT+R _
 set DCU_DATA_NEG_PINS  [remove_from_collection [get_pins core/cacheMMUSch/DCU_data_NEG*] \
-                                               [get_pins "core/cacheMMUSch/DCU_data_NEG[16] \
-                                                          core/cacheMMUSch/DCU_data_NEG[17] \
-                                                          core/cacheMMUSch/DCU_data_NEG[18]"]]
+                                               [get_pins "core/cacheMMUSch/DCU_data_NEG<16> \
+                                                          core/cacheMMUSch/DCU_data_NEG<17> \
+                                                          core/cacheMMUSch/DCU_data_NEG<18>"]]
 set OCMDATA_NEG_PINS [get_pins core/cpu_topSch/exe_topSch/loadSteeringSch/OCM_dsData*]

 set_false_path -through $DCU_DATA_NEG_PINS -through [get_pins core/cpu_topSch/exe_topSch/loadSteeringSch/gprLpIn*]
@@ -83,11 +86,11 @@
 # Input of the mux(s) are DCU_data_NEG*
 #
 for {set x 0} {$x<32} {incr x} {
-  set_false_path -through core/cpu_topSch/exe_topSch/loadSteeringSch/DCU_data_NEG[$x] \
+  set_false_path -through core/cpu_topSch/exe_topSch/loadSteeringSch/DCU_data_NEG<$x> \
                         -through [get_pins core/cpu_topSch/exe_topSch/loadSteeringSch/dRegBypass*]
 }
 for {set x 0} {$x<32} {incr x} {
-  set_false_path -through core/cpu_topSch/exe_topSch/loadSteeringSch/DCU_data_NEG[$x] \
+  set_false_path -through core/cpu_topSch/exe_topSch/loadSteeringSch/DCU_data_NEG<$x> \
                        -through [get_pins core/cpu_topSch/exe_topSch/loadSteeringSch/gprLpIn*]
 }

diff -ru ../../IBM/DW_ppc405-FS_iv_1.0a_AV/dc/constraints/PPC405F5V1_test.cons ./dc/constraints/PPC405F5V1_test.cons
--- ../../IBM/DW_ppc405-FS_iv_1.0a_AV/dc/constraints/PPC405F5V1_test.cons       2005-10-17 16:31:05.000000000 +0100
+++ ./dc/constraints/PPC405F5V1_test.cons       2009-11-10 23:17:36.560210767 +0000
@@ -3,6 +3,9 @@
 #
 #  Copyright (c) International Business Machines Corporation, 2005.
 #
+#  Modified by Dr Matthew Swabey matthew@swabey.org to support the modern
+#  synopsys design tools and techniques.
+#
 #  This file contains trade secrets and other proprietary and confidential
 #  information of International Business Machines Corporation which are
 #  protected by copyright and other intellectual property rights and shall
@@ -17,13 +20,17 @@
 #
 # This file sets up the scan constraints
 #
+
 #============================================================================
 # Create Test Clocks
 #============================================================================
-create_test_clock CPMC405CLOCK        -waveform {60.0 70.0} -period 100.0
-create_test_clock CPMC405PLBSYNCCLOCK -waveform {60.0 70.0} -period 100.0
-create_test_clock JTGC405TCK          -waveform {60.0 70.0} -period 100.0
-create_test_clock TESTC405BISTCE0STCLK -waveform {60.0 70.0} -period 100.0
+
+set_dft_signal -view existing_dft -type ScanClock -port CPMC405CLOCK -timing [list 60.0 70.0]
+set_dft_signal -view existing_dft -type ScanClock -port CPMC405PLBSYNCCLOCK -timing [list 60.0 70.0]
+set_dft_signal -view existing_dft -type ScanClock -port JTGC405TCK -timing [list 60.0 70.0]
+set_dft_signal -view existing_dft -type ScanClock -port TESTC405BISTCE0STCLK -timing [list 60.0 70.0]
+
+#set_dft_equivalent_signals [list CPMC405CLOCK CPMC405PLBSYNCCLOCK JTGC405TCK TESTC405BISTCE0STCLK]

 #============================================================================
 #    Define scan ports
@@ -33,20 +40,14 @@
 set test_scan_in_port_naming_style "scan_in%s"
 set test_scan_out_port_naming_style "scan_out%s"

-## DFT DRC currently (2003.12) has a problem infering resets, so do it explicitly
-#if {[get_ports -quiet test_async_rst_n] == ""} {create_port test_async_rst_n}
-#set_signal_type test_async_inverted test_async_rst_n
+set_dft_signal -view existing_dft -type TestMode -port [get_port TESTC405TESTMODE] -active_state 1
+set_dft_signal -view existing_dft -type ScanEnable -port [get_port TESTC405SCANENABLE] -active_state 1
+set_dft_signal -view spec -type ScanEnable -port [get_port TESTC405SCANENABLE] -active_state 1

-set_dft_signal  test_mode        -port TESTC405TESTMODE
-set_scan_signal test_scan_enable -port TESTC405SCANENABLE
 for {set x 0} {$x<8} {incr x} {
-       set_scan_signal test_scan_in     -port TESTC405SCANIN${x}
-       set_scan_signal test_scan_out    -port C405TESTSCANOUT${x}
+       set_dft_signal -view spec -type ScanDataIn -port [get_port TESTC405SCANIN${x}]
+       set_dft_signal -view spec -type ScanDataOut -port [get_port C405TESTSCANOUT${x}]
 }
-#for {set x 0} {$x<32} {incr x} {
-#      set_scan_signal test_scan_in     -port TESTC405SCANIN${x} -chain scan${x}
-#      set_scan_signal test_scan_out    -port C405SCANOUT${x} -chain scan${x}
-#}

 #============================================================================
 #    Set up test protocol
@@ -68,16 +69,16 @@
 set_scan_element false [get_cell core/cacheMMUSch/icu_topSch/icuRamDataFlow/tagArray_Sch/icu_tag/tagSram]

 # Assert these input ports to specified values during test mode
-set_signal_type "test_asynch" RSTC405RESETCORE
-set_test_hold 1 TESTC405BISTCE1MODE
-set_test_hold 1 TESTC405BISTCE1ENABLE
-set_test_hold 1 TIEC405CLOCKENABLE
-set_test_hold 1 TIEC405DUTYENABLE
-set_test_hold 1 TESTC405TESTMODE
-set_test_hold 1 JTGC405TRSTNEG
-set_test_hold 1 CPMC405CPUCLKENCCLK
-set_test_hold 1 CPMC405TIMERCLKENCCLK
-set_test_hold 1 CPMC405JTAGCLKENCCLK
+set_dft_signal -view existing_dft -type Reset -port -active_state 1 [get_port RSTC405RESETCORE]
+set_dft_signal -view existing_dft -type Constant -active_state 1 -port [get_port TESTC405BISTCE1MODE]
+set_dft_signal -view existing_dft -type Constant -active_state 1 -port [get_port TESTC405BISTCE1ENABLE]
+set_dft_signal -view existing_dft -type Constant -active_state 1 -port [get_port TIEC405CLOCKENABLE]
+set_dft_signal -view existing_dft -type Constant -active_state 1 -port [get_port TIEC405DUTYENABLE]
+set_dft_signal -view existing_dft -type Constant -active_state 1 -port [get_port TESTC405TESTMODE]
+set_dft_signal -view existing_dft -type Constant -active_state 1 -port [get_port JTGC405TRSTNEG]
+set_dft_signal -view existing_dft -type Constant -active_state 1 -port [get_port CPMC405CPUCLKENCCLK]
+set_dft_signal -view existing_dft -type Constant -active_state 1 -port [get_port CPMC405TIMERCLKENCCLK]
+set_dft_signal -view existing_dft -type Constant -active_state 1 -port [get_port CPMC405JTAGCLKENCCLK]

 ## Set the default test parameters
 set test_default_period        100
@@ -88,19 +89,21 @@

 set test_stil_netlist_format verilog

-set_dft_optimization_configuration -preserve_design_name true
+set_dft_insertion_configuration -preserve_design_name true
 set_scan_configuration -style multiplexed_flip_flop
-set_scan_configuration -methodology full_scan
-set_scan_configuration -dedicated_scan_ports true
+set_scan_configuration -create_dedicated_scan_out_ports true
 set_scan_configuration -add_lockup true
 set_scan_configuration -clock_mixing mix_clocks
-set_scan_configuration -rebalance false
-set_scan_configuration -internal_clocks false
+set_scan_configuration -internal_clocks none
 set_scan_configuration -hierarchical_isolation false
 set_scan_configuration -create_test_clocks_by_system_clock_domain false
-set_scan_configuration -disable true
-set_scan_configuration -bidi input
-set_scan_configuration -insert_end_of_chain_lockup_latch true
+#set_scan_configuration -disable true
+set_dft_configuration -fix_bidirectional enable
+set_dft_configuration -fix_clock enable
+set_dft_configuration -fix_reset enable
+set_dft_configuration -fix_bus enable
+#set_scan_configuration -insert_end_of_chain_lockup_latch true
+set_scan_configuration -insert_terminal_lockup true

 ## Need to specify the number of chains.
 set_scan_configuration -chain_count 8
@@ -108,5 +111,5 @@

 # set the latches in the design to transperent mode
 # Make sure that your latch variable is set in the setup.tcl file
-set_scan_transparent true ${LIBRARY_NAME}/$LATCH_NAMES -existing
+#set_scan_transparent true ${LIBRARY_NAME}/$LATCH_NAMES -existing

diff -ru ../../IBM/DW_ppc405-FS_iv_1.0a_AV/dc/run_compile.csh ./dc/run_compile.csh
--- ../../IBM/DW_ppc405-FS_iv_1.0a_AV/dc/run_compile.csh        2005-10-17 16:31:05.000000000 +0100
+++ ./dc/run_compile.csh        2009-11-09 18:08:54.904611366 +0000
@@ -3,6 +3,9 @@
 # **************************************************************************
 #
 #  Copyright (c) International Business Machines Corporation, 2004.
+#
+#  Modified by Dr Matthew Swabey matthew@swabey.org to support the modern
+#  synopsys design tools and techniques.
 #
 #  This file contains trade secrets and other proprietary and confidential
 #  information of International Business Machines Corporation which are
@@ -43,6 +46,7 @@
 setenv scan_switch true
 setenv bist_switch false
 setenv ultra_switch false
+setenv topo_switch false
 setenv high_switch false
 setenv Test_lic true
 setenv Power_lic true
@@ -55,6 +59,7 @@
    echo "  -synth       : synthesize; will elaborate if elab switch is on or no elab db exists"
    echo "  -dft         : Stitches scan chain; valid only if a synthesis is completed first"
    echo "  -ultra       : use Ultra options that require an Ultra-Opt license"
+   echo "  -topo        : use Topographical synthesis"
    echo "  -high        : high effort compile"
    echo "  -bist        : Add Memory BIST to the design"
    echo "  -no_scan     : Do not use -scan with the compile options that require a Test-Compiler license"
@@ -100,6 +105,9 @@
        case x-ultra:
            setenv ultra_switch true
            breaksw
+       case x-topo:
+           setenv topo_switch true
+           breaksw
        case x-high:
            setenv high_switch true
            breaksw
@@ -115,6 +123,7 @@
            echo "  -bist               : Add Memory BIST to the design"
            echo "  -no_scan            : Do not use -scan with the compile options that require a Test-Compiler license"
            echo "  -ultra              : use Ultra options that require an Ultra-Opt license"
+           echo "  -topo               : use Topographical synthesis"
            echo "  -no_scan            : Do not use -scan with the compile options that require an Test-Compiler license"
            echo "  -no_power           : Do not use Power Compiler to add clock gating to the design"
            echo "  -clean_all          : Deletes all reports and dbs in the pass directories"
@@ -125,6 +134,7 @@
            echo "  -synth              : synthesize; will elaborate if elab switch is on or no elab db exists"
            echo "  -dft                : Stitches scan chain; valid only if a synthesis completed first"
            echo "  -ultra              : use Ultra options that require an Ultra-Opt license"
+           echo "  -topo               : use Topographical synthesis"
            echo "  -bist               : Add Memory BIST to the design"
            echo "  -no_scan            : Do not use -scan with the compile options that require an Test-Compiler license"
            echo "  -no_power           : Do not use Power Compiler to add clock gating to the design"
@@ -167,7 +177,11 @@
      echo "Elaborating Design"
      echo "##########################################################"
      echo ""
+  if ($topo_switch == true) then
+     dc_shell-t -topo -f ./scripts/p405s_elab.tcl | tee logs/p405s_elab.log
+  else
      dc_shell-t -f ./scripts/p405s_elab.tcl | tee logs/p405s_elab.log
+  endif
      echo ""
      echo "##########################################################"
      echo "Finished Elaboration"
@@ -182,7 +196,11 @@
      echo "Synthesizing Design"
      echo "##########################################################"
      echo ""
+  if ($topo_switch == true) then
+     dc_shell-t -topo -f ./scripts/p405s_compile.tcl | tee logs/p405s_compile.log
+  else
      dc_shell-t -f ./scripts/p405s_compile.tcl | tee logs/p405s_compile.log
+  endif
      echo ""
      echo "##########################################################"
      echo "Finished Synthesis"
@@ -197,7 +215,11 @@
      echo "Stitching scan chains"
      echo "##########################################################"
      echo ""
+  if ($topo_switch == true) then
+     dc_shell-t -topo -f ./scripts/p405s_dft.tcl | tee logs/p405s_dft.log
+  else
      dc_shell-t -f ./scripts/p405s_dft.tcl | tee logs/p405s_dft.log
+  endif
      echo ""
      echo "##########################################################"
      echo "Finished Stitching scan chains"
@@ -214,6 +236,7 @@
 unsetenv scan_switch
 unsetenv bist_switch
 unsetenv ultra_switch
+unsetenv topo_switch
 unsetenv high_switch
 unsetenv Test_lic
 unsetenv Power_lic
diff -ru ../../IBM/DW_ppc405-FS_iv_1.0a_AV/dc/scripts/p405s_compile.tcl ./dc/scripts/p405s_compile.tcl
--- ../../IBM/DW_ppc405-FS_iv_1.0a_AV/dc/scripts/p405s_compile.tcl      2005-10-17 16:31:05.000000000 +0100
+++ ./dc/scripts/p405s_compile.tcl      2009-11-20 20:04:16.248225918 +0000
@@ -3,6 +3,9 @@
 #
 #  Copyright (c) International Business Machines Corporation, 2005.
 #
+#  Modified by Dr Matthew Swabey matthew@swabey.org to support the modern
+#  synopsys design tools and techniques.
+#
 #  This file contains trade secrets and other proprietary and confidential
 #  information of International Business Machines Corporation which are
 #  protected by copyright and other intellectual property rights and shall
@@ -22,6 +25,7 @@
 set scan_switch  [getenv scan_switch]
 set high_switch  [getenv high_switch]
 set ultra_switch [getenv ultra_switch]
+set topo_switch  [getenv topo_switch]

 set SCRIPT compile

@@ -49,9 +53,9 @@
 # Read in elaborated design
 #
 #=================================================================================
-       set INPUT_DB "./db/${TOPDESIGN}_elab.db"
+       set INPUT_DB "./db/${TOPDESIGN}_elab.ddc"
         if { [file readable $INPUT_DB ] == 1} {
-          read_db $INPUT_DB
+          read_ddc $INPUT_DB
         } else {
           puts "FAILURE: Failed to find $INPUT_DB"
           exit 0
@@ -94,6 +98,7 @@
 # At this point we no longer need to suppress the non-unate clock warning
 # and we want to know if it happens after the compile.
 set suppress_errors {CMD-041 TIM-134}
+
 #=================================================================================
 #
 # Uniquify
@@ -101,7 +106,7 @@
 #=================================================================================
         uniquify
        link
-       write_file -format db -hier -o ./db/${FILENAME_PREFIX}_pre_compile.db
+       write_file -format ddc -hier -o ./db/${FILENAME_PREFIX}_pre_compile.ddc

 #=================================================================================
 #
@@ -129,28 +134,29 @@
 # Compile
 #
 #=================================================================================
-       if {$ultra_switch == "true"} {
-               set_ultra_optimization true -force
+       set COMPILE_STRING ""
+        if {($Power_lic == "true")} {
+          append $COMPILE_STRING " -gate_clock"
+       }
+       if {$scan_switch == "true"} {
+          append $COMPILE_STRING " -scan"
        }

-       if {$high_switch == "true"} {
-               if {$scan_switch == "true"} {
-                       echo "** compile -scan -map_effort high **"
-                       compile -scan -map_effort high -boundary_optimization
-               } else {
-                       echo "** compile -map_effort high **"
-                       compile -map_effort high -boundary_optimization
-               }
+       if {$ultra_switch == "true" | $topo_switch == "true"} {
+          set COMPILE_STRING "compile_ultra ${COMPILE_STRING} "
+          echo "** " ${COMPILE_STRING} " **"
+          eval ${COMPILE_STRING}
        } else {
-               if {$scan_switch == "true"} {
-                       echo "** compile -scan **"
-                       compile -scan -effort medium -boundary_optimization
-               } else {
-                       echo "** compile  **"
-                       compile -effort medium -boundary_optimization
-               }
+          if {$high_switch == "true"} {
+            set COMPILE_STRING "compile ${COMPILE_STRING} -map_effort high -boundary_optimization"
+            echo "** " ${COMPILE_STRING} " **"
+            eval ${COMPILE_STRING}
+          } else {
+            set COMPILE_STRING "compile ${COMPILE_STRING} -map_effort medium -boundary_optimization"
+            echo "** " ${COMPILE_STRING} " **"
+            eval ${COMPILE_STRING}
+          }
        }
-
         current_design ${TOPDESIGN}
         link

@@ -163,9 +169,8 @@
                source ./scripts/verilog_name_rules.tcl
                verilog_name_rules
                change_names -rule verilog_name_rule -hierarchy -verbose
-               change_names -rule verilog_name_rule -hierarchy -verbose
        }
-       write_file -format db -hier -o ./db/${FILENAME_PREFIX}.db
+       write_file -format ddc -hier -o ./db/${FILENAME_PREFIX}.ddc
        write -f verilog -hier -o ./netlist/${FILENAME_PREFIX}.v

 #=================================================================================
diff -ru ../../IBM/DW_ppc405-FS_iv_1.0a_AV/dc/scripts/p405s_dft.tcl ./dc/scripts/p405s_dft.tcl
--- ../../IBM/DW_ppc405-FS_iv_1.0a_AV/dc/scripts/p405s_dft.tcl  2005-10-17 16:31:05.000000000 +0100
+++ ./dc/scripts/p405s_dft.tcl  2009-11-20 20:58:02.696428891 +0000
@@ -3,6 +3,9 @@
 #
 #  Copyright (c) International Business Machines Corporation, 2005.
 #
+#  Modified by Dr Matthew Swabey matthew@swabey.org to support the modern
+#  synopsys design tools and techniques.
+#
 #  This file contains trade secrets and other proprietary and confidential
 #  information of International Business Machines Corporation which are
 #  protected by copyright and other intellectual property rights and shall
@@ -17,6 +20,7 @@
 #=================================================================================
 # This script inserts scan
 #=================================================================================
+set high_switch  [getenv high_switch]

 #=================================================================================
 #
@@ -43,9 +47,9 @@
 # Read in elaborated design
 #
 #=================================================================================
-       set INPUT_DB ./db/${TOPDESIGN}_compile.db
+       set INPUT_DB ./db/${TOPDESIGN}_compile.ddc
         if { [file readable $INPUT_DB ] == 1} {
-          read_db $INPUT_DB
+          read_ddc $INPUT_DB
         } else {
           puts "Error: Failed to find $INPUT_DB"
           exit 0
@@ -53,7 +57,7 @@

         current_design ${TOPDESIGN}
         link
-        echo "INFO: Elaborated DB file for ${TOPDESIGN} linked at [exec date]"
+        echo "INFO: Elaborated DDC file for ${TOPDESIGN} linked at [exec date]"

         # Check the design
         echo "INFO: link and check_design output for module ${TOPDESIGN}\n" > \
@@ -82,6 +86,10 @@
 # Insert DFT
 #=================================================================================

+if {$high_switch == "true"} {
+    set_dft_insertion_configuration -map_effort high
+}
+
 insert_dft
 # check_dft  -verbose  > ./reports/${FILENAME_PREFIX}.check_dft.post.rpt
 dft_drc -verbose > ./reports/${FILENAME_PREFIX}.dft_drc.post.rpt
@@ -97,7 +105,7 @@
                change_names -rule verilog_name_rule -hierarchy -verbose
                change_names -rule verilog_name_rule -hierarchy -verbose
        }
-       write_file -format db -hier -o ./db/${FILENAME_PREFIX}.db
+       write_file -format ddc -hier -o ./db/${FILENAME_PREFIX}.ddc
        write -f verilog -hier -o ./netlist/${FILENAME_PREFIX}.v

 #=================================================================================
@@ -126,5 +134,6 @@

 date

+
 exit

diff -ru ../../IBM/DW_ppc405-FS_iv_1.0a_AV/dc/scripts/p405s_elab.tcl ./dc/scripts/p405s_elab.tcl
--- ../../IBM/DW_ppc405-FS_iv_1.0a_AV/dc/scripts/p405s_elab.tcl 2005-10-17 16:31:05.000000000 +0100
+++ ./dc/scripts/p405s_elab.tcl 2009-11-09 18:17:58.598880874 +0000
@@ -3,6 +3,9 @@
 #
 #  Copyright (c) International Business Machines Corporation, 2005.
 #
+#  Modified by Dr Matthew Swabey matthew@swabey.org to support the modern
+#  synopsys design tools and techniques.
+#
 #  This file contains trade secrets and other proprietary and confidential
 #  information of International Business Machines Corporation which are
 #  protected by copyright and other intellectual property rights and shall
@@ -21,9 +24,7 @@
 set bist_switch  [getenv bist_switch]

 set template_naming_style "%s_%p"
-set hdlin_enable_vpp TRUE
-set hdlin_preserve_vpp_files true
-set compile_delete_unloaded_sequential_cells false
+#set compile_delete_unloaded_sequential_cells false

 sh rm -rf ./ppc405
 define_design_lib ppc405 -path ./ppc405
@@ -48,16 +49,26 @@
 set TOPDESIGN $design_name
 set FILENAME_PREFIX ${TOPDESIGN}_${SCRIPT}

+
 #=================================================================================
 #
 # Read in design files
 #
 #=================================================================================
 # read all files in ppc_405s_cpu directory except the following behavioral models
-set acs_exclude_list [concat $acs_exclude_list "PPC405F5V1_soft.v SRAM_256wordsX44bits.v"]
+set RTL_SRC_PATH ../src/rtl/
+set RTL_SRC_LIST [list]
+foreach FILE [glob -nocomplain -type f -directory $RTL_SRC_PATH -tails *.v] {
+  lappend RTL_SRC_LIST $FILE
+}
+
+set RTL_SRC_LIST [ lsearch -all -inline -not -exact $RTL_SRC_LIST PPC405F5V1_soft.v ]
+set RTL_SRC_LIST [ lsearch -all -inline -not -exact $RTL_SRC_LIST SRAM_256wordsX44bits.v ]

 # if bist enabled
 if {($bist_switch == "true")} {
+       echo "NOT UPDATED YET"
+       exit
        echo "** BIST ENABLED **"
        set acs_exclude_list [concat $acs_exclude_list "p405s_DCU_parityRAM.v"]
        set acs_exclude_list [concat $acs_exclude_list "p405s_DCU_ram16K.v"]
@@ -79,9 +90,10 @@
 # if the User Specific RAMs option is set in the Configure Activity
 set memory_wrappers " "
 set memory_wrappers [concat ../src/mem_models/p405s_dataram_64X34_wrapper.v  ../src/mem_models/p405s_sram256x46_wrapper.v ../src/mem_models/p405s_sram256x48_wrapper.v ../src/mem_models/p405s_sram512x128_wrapper.v ../src/mem_models/p405s_sram512x32_wrapper.v ../src/mem_models/p405s_sram512x8_wrapper.v ../src/mem_models/p405s_sramBytWr512x128_wrapper.v]
-set acs_hdl_source [concat $memory_wrappers ../src/rtl/p405s_params.v $acs_hdl_source "../src/rtl"]
+set RTL_SRC_LIST [concat $memory_wrappers ../src/rtl/p405s_params.v $RTL_SRC_LIST]

-acs_read_hdl -recurse -format verilog -library ppc405 -verbose $TOPDESIGN -no_elaborate
+lappend search_path ../src/rtl
+analyze -library ppc405 -format verilog $RTL_SRC_LIST

 #=================================================================================
 #
@@ -133,28 +145,14 @@
 # Elaborate the design
 #
 #=================================================================================
-if {($Power_lic == "true")} {
-  elaborate -library ppc405 -gate_clock $TOPDESIGN
-} else {
-  elaborate -library ppc405 $TOPDESIGN
-}

-#=================================================================================
-#
-# Connect the scan enable port to control the gated clock cells
-#
-#=================================================================================
-if {($Power_lic == "true")} {
-   set_scan_signal test_scan_enable -port [get_port TESTC405SCANENABLE]
-   set_dft_signal test_mode         -port [get_port TESTC405TESTMODE]
-   hookup_testports -verbose
-}
+elaborate -library ppc405 $TOPDESIGN

 #=================================================================================
 #
 # Write out elaborated design
 #
 #=================================================================================
-write -f db -hier -o $acs_work_dir/db/${FILENAME_PREFIX}.db
+write -f ddc -hier -o ./db/${FILENAME_PREFIX}.ddc

 exit
diff -ru ../../IBM/DW_ppc405-FS_iv_1.0a_AV/dc/scripts/p405s_zerowlm.tcl ./dc/scripts/p405s_zerowlm.tcl
--- ../../IBM/DW_ppc405-FS_iv_1.0a_AV/dc/scripts/p405s_zerowlm.tcl      2005-10-17 16:31:05.000000000 +0100
+++ ./dc/scripts/p405s_zerowlm.tcl      2009-11-20 20:04:35.505970139 +0000
@@ -45,9 +45,9 @@
 # Read in elaborated design
 #
 #=================================================================================
-       set INPUT_DB "./db/${TOPDESIGN}_elab.db"
+       set INPUT_DB "./db/${TOPDESIGN}_elab.ddc"
         if { [file readable $INPUT_DB ] == 1} {
-          read_db $INPUT_DB
+          read_ddc $INPUT_DB
         } else {
           puts "FAILURE: Failed to find $INPUT_DB"
           exit 0
@@ -55,7 +55,7 @@

         current_design ${TOPDESIGN}
         link
-        echo "INFO: Elaborated DB file for ${TOPDESIGN} linked at [exec date]"
+        echo "INFO: Elaborated DDC file for ${TOPDESIGN} linked at [exec date]"

         # Check the design
         echo "INFO: link and check_design output for module ${TOPDESIGN}\n" > \
@@ -104,7 +104,7 @@
 #=================================================================================
         uniquify
        link
-       write_file -format db -hier -o ./db/${FILENAME_PREFIX}_pre_compile.db
+       write_file -format ddc -hier -o ./db/${FILENAME_PREFIX}_pre_compile.ddc

 #=================================================================================
 #
@@ -159,7 +159,7 @@
                change_names -rule verilog_name_rule -hierarchy -verbose
        }
        write -f verilog -hier -o ./netlist/${FILENAME_PREFIX}.v
-       write_file -format db -hier -o ./db/${FILENAME_PREFIX}.db
+       write_file -format ddc -hier -o ./db/${FILENAME_PREFIX}.ddc

 #=================================================================================
 #
diff -ru ../../IBM/DW_ppc405-FS_iv_1.0a_AV/dc/scripts/setup.tcl ./dc/scripts/setup.tcl
--- ../../IBM/DW_ppc405-FS_iv_1.0a_AV/dc/scripts/setup.tcl      2005-10-17 16:31:05.000000000 +0100
+++ ./dc/scripts/setup.tcl      2009-11-09 18:17:58.609879585 +0000
@@ -3,6 +3,9 @@
 #
 #  Copyright (c) International Business Machines Corporation, 2005.
 #
+#  Modified by Dr Matthew Swabey matthew@swabey.org to support the modern
+#  synopsys design tools and techniques.
+#
 #  This file contains trade secrets and other proprietary and confidential
 #  information of International Business Machines Corporation which are
 #  protected by copyright and other intellectual property rights and shall
@@ -10,7 +13,7 @@
 #  or used for any purpose except as specifically authorized in writing by
 #  International Business Machines Corporation. This notice must be
 #  contained as part of this text at all times.
-#
+#
 # **************************************************************************
 #
 #===========================================================================
@@ -128,30 +131,46 @@
 #  create the MilkyWay database.
 #----------------------------------------------------------------------------
 set lib_path ../tech_lib
-#set MW_REF_LIB [list ${lib_path}/artisan_13lvfsg/astro/artisan_13lvfsg_mdb \
-#                     ${lib_path}/artisan_13lvfsg/syn/dataram_64X34 \
-#                     ${lib_path}/memories/artisan_13lvfsg/mdb/sram256x46 \
-#                     ${lib_path}/memories/artisan_13lvfsg/mdb/sram256x48 \
-#                     ${lib_path}/memories/artisan_13lvfsg/mdb/sram512x128 \
-#                     ${lib_path}/memories/artisan_13lvfsg/mdb/sram512x32 \
-#                     ${lib_path}/memories/artisan_13lvfsg/mdb/sram512x8 \
-#                     ${lib_path}/memories/artisan_13lvfsg/mdb/sramBytWr512x128 ]
+set MW_REF_LIB [list ${lib_path}/artisan_13lvfsg/astro/artisan_13lvfsg_mdb \
+                     ${lib_path}/artisan_13lvfsg/syn/dataram_64X34 \
+                     ${lib_path}/memories/artisan_13lvfsg/mdb/sram256x46 \
+                     ${lib_path}/memories/artisan_13lvfsg/mdb/sram256x48 \
+                     ${lib_path}/memories/artisan_13lvfsg/mdb/sram512x128 \
+                     ${lib_path}/memories/artisan_13lvfsg/mdb/sram512x32 \
+                     ${lib_path}/memories/artisan_13lvfsg/mdb/sram512x8 \
+                     ${lib_path}/memories/artisan_13lvfsg/mdb/sramBytWr512x128 ]
 set MW_TECH_FILE ${lib_path}/artisan_13lvfsg/apollo/tf/tsmc13fsg_hs_6lm.tf
-set MAX_TLUPLUS ${lib_path}/star-rc/t013s6ml_lowklv.tluplus
-set NOM_TLUPLUS ${lib_path}/star-rc/t013s6ml_lowklv.tluplus
-set MIN_TLUPLUS ${lib_path}/star-rc/t013s6ml_lowklv.tluplus
-set MAP_FILE    ${lib_path}/star-rc/plib2itf.map
-#
+
+set MW_DESIGN_LIBRARY ./mw.db
+
+echo $MW_REF_LIB
+
+if {$synopsys_program_name == "dc_shell"}  {
+  if {[shell_is_in_topographical_mode]} {
+    if {[expr {![file isdirectory $MW_DESIGN_LIBRARY ]}]} {
+      echo "INFO: Milkyway libary not found. Creating a new one."
+      create_mw_lib -technology $MW_TECH_FILE -mw_reference_library $MW_REF_LIB $MW_DESIGN_LIBRARY
+    }
+    open_mw_lib $MW_DESIGN_LIBRARY
+    check_library
+  }
+}
+
 #----------------------------------------------------------------------------
 # Use TLUPlus for RC Computation
-# If you do not have TLUPlus, Comment out the following lines
+# If you do not have TLUPlus, Comment out the following
 #----------------------------------------------------------------------------
-# -tech2itf_map  $MAP_FILE
+set MAX_TLUPLUS ${lib_path}/star-rc/t013s6ml_lowklv.tluplus
+set NOM_TLUPLUS ${lib_path}/star-rc/t013s6ml_lowklv.tluplus
+set MIN_TLUPLUS ${lib_path}/star-rc/t013s6ml_lowklv.tluplus
+set MAP_FILE    ${lib_path}/star-rc/tf2itf.map
+
 if { [info exists synopsys_program_name] } {
-   if { [regexp {^psyn} $synopsys_program_name] } {
+   if { [regexp {^psyn} $synopsys_program_name] | [shell_is_in_topographical_mode] } {
        set_tlu_plus_files -max_tluplus $MAX_TLUPLUS \
                         -min_tluplus $MIN_TLUPLUS \
-                       -plib2itf_map $MAP_FILE
+                       -tech2itf_map $MAP_FILE
+       check_tlu_plus_files
    }
 }

5) Save this file as fix_dc.diff in the same directory as the script - they must be in the same directory for this to work.

6) Open a terminal and cd into the top of the workspace you have created. Execute the script and you should see the following output:

patching file ./dc/constraints/PPC405F5V1_functional.cons
patching file ./dc/constraints/PPC405F5V1_test.cons
patching file ./dc/run_compile.csh
patching file ./dc/scripts/p405s_compile.tcl
patching file ./dc/scripts/p405s_dft.tcl
patching file ./dc/scripts/p405s_elab.tcl
patching file ./dc/scripts/p405s_zerowlm.tcl
patching file ./dc/scripts/setup.tcl

7) cd into the dc directory of your workspace and run the following command: ./run_compile.csh -elab -synth -dft

8) Eventually you should have a lovely PowerPC™ 405 gate level netlist in ./dc/netlist ...

9) ...

10) Profit!

Published with permission from IBM and Synopsys

Friday, 6 November 2009

IBM PowerPC™ 405-S: Verification of the RTL with the supplied Artisan SRAMs

[Please note that these instructions reference the 1.00a version of the Synopsys PowerPC™ 405-S coreKit which is the version provided in the University IP package from IBM. There are updated versions available from Synopsys that address several of the issues outlined below. These are specifically commented on where known.]

This is the second article in the series (click here for the series index) describing the IBM PowerPC™ 405 synthesizable core and peripherals and will cover what needs to be done to take the IP and get the RTL simulating with the modern versions of the necessary Synopsys Tools and a simulator of your choice.

Initial Unpacking
When you first unpack the DesignWare PowerPC405-S™ implementation view coreKit (the archive is called DW_ppc405-FS_iv_1.0a_AV.tar.gz) it expands to a directory DW_ppc405-FS_iv_1.0a_AV.

The first thing you should do is begin reading the excellently written User Guide (docs/405_ivug.pdf) which provides the suggested flows along with the Release Note (docs/iv_rn.pdf) that specifies the tools and environment with which you need to build the processor.

However the software versions requested by the release note to simulate the RTL is problematic. I have listed below the required software in black, the lowest version available in red and the highest version available at time of writing in blue:

Required:
  1. Synopsys coreConsultant, Version V-2004.03-CT4.4.2 Z-2007.06-SP5 C-2009.06-3
  2. Synopsys Vera System Verifier, Version 6.3.0 Z-2006.12 A-2007.12-12
  3. Synopsys Design Compiler, Version U-2004.06-SP2 Z-2007.03-SP2 C-2009.06-SP2
One of:
  1. Synopsys VCS, Version 7.1 Y-2006.06-SP1 C-2009.06-1
  2. Mentor Graphics ModelSim, Version 5.7g 6.5c
  3. Cadence NC-Verilog, Version 5.1 8.1
As you can see the specified tool versions are simply not available.
[Note: at the time of publication the current commercial coreKit is version 3, not the version 1.0a discussed here and supports the current generation of tools.]

In the following sections I will describe how to get the PowerPC 405 verified with the following tool set:
  1. coreTools C-2009.06
  2. DC Ultra B-2008.09
  3. DesignWare 2009.06a
  4. vera A-2007.12
  5. NC-Verilog (Integrated Unified Simulator) 8.1
Before you proceed further be sure that all the necessary environment variables from the documentation are set and the correct executables are the in the path.

Getting Started

The educational distribution doesn't come packaged as a single coreKit file but as a compressed, already installed, coreKit directory. To get started fire up coreConsultant and select File > New Workspace. Point the installed coreKit path at the unpacked .tar.gz and choose a directory as the root and a new name for the Workspace. In the following examples we will use the workspace RTLVerification created in the same directory as the unpacked coreKit.

You should now have a directory tree in this root beginning with the name of the workspace. It is similar to the unpacked .tar.gz and populated with symlinks to some of the original files.

Choose the built in Artisan 130LVFSG RAM models and proceed to the simulation stage (I will discuss integrating custom SRAMs in a later article).

Verification by Simulation: Initial Experiences

When you have successfully moved onto the "Verify Component" stage things are not so simple. As we are going to use NC Verilog be sure to choose NC_Verilog as the simulator and ensure the relevant paths are set correctly. Leave the rest of the options at their default values.

[Note: All the issues listed here (and some more of the same) are solved with one comprehensive script and a few instructions in the section below. This section is here to detail what kind of issues you may face and how to solve them to allow you to debug your own installations should this be necessary.]

Building the Vera Objects

The design of the simulation/test environment uses Vera testbench tool to provide compiled simulation objects that surround the Verilog core and a few other Verilog modules and test vectors. We need to compile these Vera objects and we do that by opening a terminal in the Workspace directory we have created (RTLVerification). Then execute this series of commands in the terminal:

cd sim/vera/src

./build_vro


The script will generate several screens full of output with no errors (a few warnings do appear). You can check the content of the sim/vera/lib directory and see the compiled .vro objects.

Running the Simulation

When you hit "simulate" you are faced with the following error message:

For some reason several script files are not correctly linked into the RTLVerification/sim/ directory, but it is easy to fix.

Open the terminal and navigate into the sim/ directory:

cd sim/
ln -s ../../DW_ppc405-FS_iv_1.0a_AV/sim/build_pli_* ./
[Note that you must have the directories setup as discussed or change the command to where the you unpacked the original coreKit directory]

Unfortunately we are not quite out of the woods yet, as the build_pli_nc.sh has to be run by hand to build the binary link between Vera and NC_Verilog. If your environment variables are set correctly then this will complete without error leaving behind the binary file libpli.so.

[Note that you need to have a 64 bit version of Vera for a 64 bit simulator and 32 bit for 32 bit. If you are building for a 32 bit simulator and 32 bit Vera on 64 bit linux edit the pli script to add an -m32 immediately after "gcc" in the compile line and "gcc" in the link line, e.g.:

elif [ `uname` = "Linux" ]; then
     gcc -m32 -fPIC -c -I$VERA_HOME/lib/vlog -I$CDS_INST_DIR/tools/verilog/include $VERA_HOME/lib/vlog/veriuser.c
     gcc -m32 -shared -o libpli.so veriuser.o $VERA_HOME/lib/vlog/libSysSciTaskpic.a
]

Retrying the simulation in the coreConsultant GUI produces the following result almost instantly:

Now I think NC Verilog is an excellent simulator however simulating an entire core in a few seconds? No.

Delving into the scripts reveals another missing file: sim/runtest. By using the same procedure as before we can link it in:

cd sim/
ln -s ../../DW_ppc405-FS_iv_1.0a_AV/sim/runtest ./

Unfortunately this script is also not in a working condition: It depends on the perl distributed by Synopsys but it is hardcoded to try one only available within IBM. However fortunately Synopsys ships this perl with coreTools. Open the file sim/runtest in your favorite text editor and change the first few lines from:

#!/afs/raleigh/cadtools/synopsys/dc/2005.09/linux/bin/snpsperl
require 5.004;
BEGIN { @INC = ( "/afs/raleigh/cadtools/synopsys/dc/2005.09/linux/lib" ); }

to:

#!$YOUR_PATH_TO_CORETOOLS/linux/dware/bin/snpsperl

require 5.004;

BEGIN { @INC = ( "$YOUR_PATH_TO_CORETOOLS/linux/dware/lib" ); }

replacing "$YOUR_PATH_TO_CORETOOLS" with the absolute path in your installation.

Trying to simulate again produces the "instant success" we will come to know and love.

Another missing file that needs to be linked into our workspace is the Makefile used to run these simulations:

cd sim/
ln -s ../../DW_ppc405-FS_iv_1.0a_AV/sim/Makefile ./

Unfortunately this Makefile has a similar problem with hardcoded paths that need correcting, as does Report.pl, runTB and hexFormal.pl. There are also numerous files that are not linked in. These issues arise from the coreKit being delivered in an installed from compressed into an archive rather than as a .coreKit file. To save you the effort of solving every one of these issues have a look at the next section. :

Verification by Simulation: Solved
[Ensure you have followed the instructions in "Getting Started" above. You should have installed a new workspace and have completed "Specify Configuration" and moved onto "Verify the Component"]

1) Open your favorite text editor and paste in the following script:

#!/bin/bash
#
# fix_sim_dir.sh
#
#Copyright Matthew Swabey (matthew@swabey.org).
#
#You are licensed to use this file in conjunction with the IBM PowerPC 405 coreKit and to make modifications as needed to this script as long as this copyright notice is kept.

#This script should be executed from the the new workspace directory after you have installed it with coreConsultant and progressed past specifying the SRAM technology.

UNPACKED_COREKIT_DIR=/export/fastcad/disktmp/mas/IBM_PUB2/DW_ppc405-FS_iv_1.0a_AV
SNPS_PERL_EXE=/home/esdcad/software/synopsys/linux/coreTools_B-2008.12-SP1/linux/dware/bin/snpsperl
SNPS_PERL_LIB=/home/esdcad/software/synopsys/linux/coreTools_B-2008.12-SP1/linux/dware/lib

#Build the vera objects with the version of vera installed
cd ./sim/vera/src
./build_vro
cd ../../..

#Link in the files needed to build the simulation of the PPC and run the testbenches
ln -s $UNPACKED_COREKIT_DIR/sim/build_pli_* ./sim/
ln -s $UNPACKED_COREKIT_DIR/sim/Makefile ./sim/
ln -s $UNPACKED_COREKIT_DIR/sim/runtest ./sim/
ln -s $UNPACKED_COREKIT_DIR/sim/Report.pl ./sim/
ln -s $UNPACKED_COREKIT_DIR/sim/scripts/hexFormat.pl ./sim/scripts/
ln -s $UNPACKED_COREKIT_DIR/sim/scripts/run405.config ./sim/scripts/
ln -s $UNPACKED_COREKIT_DIR/sim/scripts/runTB ./sim/scripts/
mkdir ./sim/testsuite
ln -s $UNPACKED_COREKIT_DIR/sim/testsuite/* ./sim/testsuite/
ln -s $UNPACKED_COREKIT_DIR/sim/testbench/*.v ./sim/testbench/
ln -s $UNPACKED_COREKIT_DIR/sim/testbench/*.inc ./sim/testbench/
ln -s $UNPACKED_COREKIT_DIR/src/rtl/*.v ./src/rtl/

#script files needing corrected perl paths separated by a space.
TO_BE_FIXED='./sim/Makefile /sim/runtest ./sim/scripts/hexFormat.pl ./sim/scripts/runTB ./sim/Report.pl'

function fix_perl_paths {
#Fix the afs paths for snpsperl
sed -i "s:/afs/raleigh/cadtools/synopsys/dc/2005.09/linux/bin/snpsperl:${SNPS_PERL_EXE}:g" $1
sed -i "s:/afs/raleigh/cadtools/synopsys/dc/2005.09/linux/lib:${SNPS_PERL_LIB}:g" $1
#Fix added for runTB
sed -i "s:/global/freeware/SunOS/5.8/perl-5.6.1/bin/perl:${SNPS_PERL_EXE}:g" $1

}

for file in $TO_BE_FIXED; do fix_perl_paths "$UNPACKED_COREKIT_DIR/$file"; done

#End of script

2) Edit the top three variables, UNPACKED_COREKIT_DIR, SNPS_PERL_EXE & SNPS_PERL_LIB to have the absolute paths to the appropriate executable or directory. There should be no spaces in the paths.


3) Save this file with a suitable name (e.g. fix_sim_dir.sh) in the new workspace you have created. Make the script executable using the command chmod u+x "filename". When you run it you should see an output that looks like this (but with many more Vera banners):

++---------------------------------------------------------------------++
 ||                     VERA System Verifier (TM)                       ||
 ||        Version: A-2007.12 () -- Thu Oct  8 11:35:39 2009            ||
 ||             Copyright (c) 1995-2004 by Synopsys, Inc.               ||
 ||                      All Rights Reserved                            ||
 ||                                                                     ||
 ||      For support, send email to vera-support@synopsys.com           ||
 ||                                                                     ||
 ||  This software and the associated documentation are confidential    ||
 ||  and proprietary to Synopsys Inc.  Your use or disclosure of this   ||
 ||  software is subject to the terms and conditions of a written       ||
 ||  license agreement between you, or your company, and Synopsys, Inc. ||
 ++---------------------------------------------------------------------++
Warning: async drive on skewed signal jtag_o.tdi, at 78 in ./p405s_jtag.vr
Warning: async drive on skewed signal jtag_o.tms, at 79 in ./p405s_jtag.vr
Compilation errors: 0
 ++---------------------------------------------------------------------++
 ||                     VERA System Verifier (TM)                       ||
 ||        Version: A-2007.12 () -- Thu Oct  8 11:35:39 2009            ||
 ||             Copyright (c) 1995-2004 by Synopsys, Inc.               ||
 ||                      All Rights Reserved                            ||
 ||                                                                     ||
 ||      For support, send email to vera-support@synopsys.com           ||
 ||                                                                     ||
 ||  This software and the associated documentation are confidential    ||
 ||  and proprietary to Synopsys Inc.  Your use or disclosure of this   ||
 ||  software is subject to the terms and conditions of a written       ||
 ||  license agreement between you, or your company, and Synopsys, Inc. ||
 ++---------------------------------------------------------------------++
Compilation errors: 0
 ++---------------------------------------------------------------------++
 ||                     VERA System Verifier (TM)                       ||
 ||        Version: A-2007.12 () -- Thu Oct  8 11:35:39 2009            ||
 ||             Copyright (c) 1995-2004 by Synopsys, Inc.               ||
 ||                      All Rights Reserved                            ||
 ||                                                                     ||
 ||      For support, send email to vera-support@synopsys.com           ||
 ||                                                                     ||
 ||  This software and the associated documentation are confidential    ||
 ||  and proprietary to Synopsys Inc.  Your use or disclosure of this   ||
 ||  software is subject to the terms and conditions of a written       ||
 ||  license agreement between you, or your company, and Synopsys, Inc. ||
 ++---------------------------------------------------------------------++
Compilation errors: 0
ln: `./sim/testbench//p405s_rambist_tb.v': File exists
ln: `./sim/testbench//tb_p405s_dataram_64X34_wrapper.v': File exists
ln: `./sim/testbench//tb_p405s_sram256x46_wrapper.v': File exists
ln: `./sim/testbench//tb_p405s_sram256x48_wrapper.v': File exists
ln: `./sim/testbench//tb_p405s_sram512x128_wrapper.v': File exists
ln: `./sim/testbench//tb_p405s_sram512x32_wrapper.v': File exists
ln: `./sim/testbench//tb_p405s_sram512x8_wrapper.v': File exists
ln: `./sim/testbench//tb_p405s_sramBytWr512x128_wrapper.v': File exists
ln: `./src/rtl//PPC405F5V1_soft.v': File exists

At this point the script will have built the vro objects using Vera, linked in all the missing files and corrected the paths in the scripts for you.

4) Enter the ./sim directory in the workspace and run the build_pli_nc.sh script by hand to build the binary link between Vera and NC_Verilog. If the environment variables are set correctly then this will complete without problem leaving behind the binary file libpli.so
[Note that you need to have a 64 bit version of Vera for a 64 bit simulator and 32 bit for 32 bit. If you are building for a 32 bit simulator and Vera on a 64 bit computer edit the scripts to add an -m32 immediately after "gcc" in the compile line and "gcc" in the link line:

elif [ `uname` = "Linux" ]; then
     gcc -m32 -fPIC -c -I$VERA_HOME/lib/vlog -I$CDS_INST_DIR/tools/verilog/include $VERA_HOME/lib/vlog/veriuser.c
     gcc -m32 -shared -o libpli.so veriuser.o $VERA_HOME/lib/vlog/libSysSciTaskpic.a
]

5) Return to the coreConsultant GUI, check you have selected the correct test suite, simulator and other variables and click "Apply" to be rewarded with:



This will take quite a while, so enjoy a well earned cup of tea/coffee/other until it completes:


6) Check the reports for anything interesting or anomalous

7) ...

8) Profit!

Published with permission from IBM and Synopsys

IBM PowerPC™ 405-S: Getting started

Synthesizable RTL versions of IBM's excellent embeddable PowerPC™ line of processors (the 405, 460 and the 460 FPU) are available to SoC designers from Synopsys' Star IP Program and this Star IP PowerPC™ 405-S is also available to Educators. Further embeddable PowerPC™ cores for synthesis are also available from AMCC.

In a series of articles I will show how to take the educational soft IP download, verify the 405 core and put it to work bonded to some of Synopsys' DesignWare IP.

Currently the articles in this series are:

1) Getting started with the synthesizable IBM PowerPC405™ (this article)
2) Verification of the RTL with the supplied Artisan PDK (now owned by ARM)
3) Synthesis of the RTL with the supplied Artisan PDK
4) Verification of the Gate Level Netlist


It was with great excitement that I received the educational IP by electronic transfer. As is typical with this kind of IP the full details remain secret until the licenses are signed, but with the kind permission of IBM and Synopsys let me lift the veil a little bit for you:

Here is what you get:
  1. Synopsys PowerPC™ 405-S Design View CoreKit v1.00a - This enables full, accurate simulations to be carried out to allow evaluation of the core running a software stack
  2. Synopsys PowerPC™ 405-S Implementation View CoreKit v1.00a - This bundle contains the verilog RTL of the actual core itself along with a demonstration technology library and the verification tools to enable its functionality to be fully exercised and guaranteed. This view also contains implementation scripts to build the design from RTL through synthesis, DFT, floorplanning, placement and clock tree expansion.
  3. Specifications - An essential set of manuals describing the exact operation of the core
  4. DDR2 Memory Controller - IBM's PLB DDR2 SDRAM memory controller to allow attachment of off chip SDRAM
  5. SRAM Memory Controller - This allows a number of internal SRAM (not SDRAM!) blocks to be presented as one continuous memory space on the PLB bus to a master
  6. PCIX Controller - IBM's PLB to PCIX controller
  7. PLB Crossbar Arbiter - This enables the connection of a large number of PLB masters to one or more slave busses. With this block very complex multicore/multimaster bus structures can be created within an SoC
  8. DMA Controller - a standard component allowing DMA transfers between peripherals and memory and vice versa
  9. UIC Controller - This is the Universal Interrupt Controller, an essential device for any SoC 
  10. PLB to AHB Bridge - This is bundled in with the core but is well worth noting - this allows the use of DesignWare IP blocks which are based around the AMBA bus specification
  11. Artisan PDK - For simulation purposes an Artisan 130nm LV PDK is supplied
  12. IBM RISCWatch - A JTAG debugger to allow full trace and debugging functions on the PowerPC core
As you can see it is an embarrassment of riches - a near complete set of IP enabling a basic single core to a complex multicore PowerPC™ 405 based SoC to be realized with only the basic IO IPs outstanding (e.g. no serial port or GPIO).

Again I should like to say a heartfelt thankyou to IBM and Synopsys for making this IP available to Universities to drive our research and educational programs forward. It is also available to drive commercial embedded designs forward after licensing.

Note: As it is a Synopsys Star IP this distribution is designed for a number of industry standard simulators and the Synopsys Implementation and Signoff tool suite. The package contains pure Verilog RTL so it is technically possible to use another vendor's synthesis tool but that is well outside the scope of this series of articles (as well as being a very big job).

Published with permission from IBM and Synopsys

Wednesday, 4 November 2009

How to Re-Analyze the DesignWare Building Blocks in Synopsys Design Compiler

Design Compiler, sometimes misnamed as dc_shell, includes a selection of datapath primitives called DesignWare Building Blocks (DWBB). Sometimes after a patch or new installation you may find these complaints in your logs:

Error:   Source file for 'DW01_SUB' was not analyzed by this release of the compiler; re-analyze it. (ELAB-343)
Error:   Source file for 'DW01_DEC' was not analyzed by this release of the compiler; re-analyze it. (ELAB-343)
Error:   Source file for 'DW01_INC' was not analyzed by this release of the compiler; re-analyze it. (ELAB-343)
Error:   Source file for 'DW01_ADD' was not analyzed by this release of the compiler; re-analyze it. (ELAB-343)
Error:   Source file for 'DW01_INC' was not analyzed by this release of the compiler; re-analyze it. (ELAB-343)
Error:   Source file for 'DW01_INC' was not analyzed by this release of the compiler; re-analyze it. (ELAB-343)
Error:   Source file for 'DW01_ADD' was not analyzed by this release of the compiler; re-analyze it. (ELAB-343)
Error:   Source file for 'DW01_INC' was not analyzed by this release of the compiler; re-analyze it. (ELAB-343)
Error:   Source file for 'DW01_INC' was not analyzed by this release of the compiler; re-analyze it. (ELAB-343)

They mean the compiled DWBB library is now out of date in relation to the version of Design Compiler you have. To cure them cd to $SYNOPSYS, then

cd dw/scripts/
./dw_analyze_syn.csh

and pretty soon you will have a lovely, shiny, new set of DesignWare Building Blocks!

[Note that this information also applied to VCS but use
cd dw/scripts/
./dw_analyze_sim.csh
]

Friday, 25 September 2009

"Transmute" - Design Philosopies

I realized that I had forgotten to describe a very, very important step: Philosophy. In this case I am using the word incorrectly. It is actually World View that I mean. From Wikipedia:
"A comprehensive world view (or worldview) is the fundamental cognitive orientation of an individual or society encompassing natural philosophy, fundamental existential and normative postulates or themes, values, emotions, and ethics."
Now what has this to do with chip design? Well you might ask! In this case it is the fundamental underpinnings and assumptions that surround the design.

The world view is formed from facts and opinions and our emotional reaction to them.

So here is the list of suitable facts for the "Transmute" project:
  • We have only built cell based custom digital cores
  • None of our typical projects are as large as this
  • The design flows are not stable - considerable development will be required
  • Several custom digital modules will be required to interfaced to licensed IP
  • We can experiment with power saving strategies
  • We are very experienced with custom analogue blocks
What, as a designer, is my emotional reaction to this? Simply this: Excitement and Concern. There are a lot of unknowns.

Hence our design World View (although a different design will have a different world view):

  • Digitally Conservative
  • Analogue Progressive
One you articulate this World View clearly you realize that this is the guide for your choices, in our case:
  • Hard IP: Eliminates the risk from core synthesis
  • Digital part to be separable from the analogue part so we can drive them separately. This will minimize the cost in case of failure or error - we would get at least one working part from the chip
  • Digital power saving strategies to be applied only after a high confidence in non-power saving digital structures obtained
  • It must be possible to disable the digital power saving structures if they are added
  • Flow decisions should favour tools which we have experience with
These decisions then guide the rest of the design flow. Also new choices can be matched against the worldview ensuring consistency.

Just bear in mind, your world view for this design may need modifying as the project progresses however if it does then you need to reconsider most of the work you have already carried out. This is typically far more important if your original plan was aggressive and you move to conservative - check work and assumptions already made!

Wednesday, 16 September 2009

The next SoC design - working title "Transmute" begins

I have a fun new hobby - designing the digital part of a new, mixed signal SoC which we are building here. It is my intention to blog the full design flow discussing the various challenges and issues as we encounter them.

Design Basics
  • Foundry
  • Technology
  • IP
  • Flow
The importance of these choices of these depends on the following thoughts:
  • What have we done before
  • Who have we worked with before
  • What have we got that works
  • What we need to do and what we would like to do
Planning a chip begins after you decide the basics above, i.e. foundry, technology and the needed parts and finally tool support. Sometimes in industry you have the luxury of a couple of other choices e.g.:
  • Cell library (we use the ST supplied one but there are others, Faraday for example)
Basic Overview Spec
  1. Two full custom ADCs for testing and evaluation
  2. A single core SoC to test our mixed signal integration and apply tests
  3. Simple connectivity to the SoC
Initial Decisions

In our case after some mulling over our experiences we decided on:
  1. ST Microelectronics via the Circuits Multi-Projets MPW broker
  2. Their HCMOS9 130nm process
  3. IP Blocks (see below)
  4. The flow, more on that later
 IP Blocks

As a university our access to IP is somewhat limited. Making a SoC requires quite a few modules like memory controllers etc.

However to the rescue rides Synopsys' DesignWare Library. It includes a basic selection of AMBA AHB/APB bus connected peripheral set and a memory controller which supports SDRAM and Flash.

To drive the the DesignWare library is the coreTools GUI (which is surprisingly hard to find) which in a nice graphical environment enables you to construct AMBA bus structures containing DesignWare peripherals. So this drives our choice of some of the tools (coreTools and DesignCompiler Ultra) as well as their DesignWare basic IP.

Onto a much more interesting question. What core to use? Considering our other IP is AMBA an ARM is the most likely choice however there are others we might use:
  • The LEON3 from Aeroflex is a Opensource (GPL), VHDL 32 bit SPARCv8 CPU with an AMBA bus. It is, however, very much bound to its peripheral library and autoconfiguration so would take a lot of work. It would also need to be customised to use the HCMOS9 SRAM blocks
  • The IBM PPC 405 is a 32 bit PowerPC core designed for embedding which is licensed to universities for teaching and education. It is the distribution created for the Synopsys flow which allows easy integration with AMBA peripherals. It is a softcore, i.e. it would need to be synthesised from RTL
In this case we wish to reduce our risk and design effort. Licensable from CMP is a foundry guaranteed ARM946E-S hard IP (i.e. they have already synthesized it and checked it) on their 130nm process. So we are going ahead with DesignWare soft IP surrounding a hard IP ARM946E-S. The benefits of hard IP are that ST have de-risked the design for us.

The features of the ARM946E-S are:
  • Excellent compiler/OS/application support. ARM is one of the best supported architectures in both Opensource and commercial software
  • Small and quick, approximately 3mm2 and clocking at 200MHz (both of these are significantly derated estimates at this stage of the design
  • MMU allowing full OS support
In addition we need the following types of IP:
  • A PLL - this is pretty much required for any SoC these days (available from CMP)
  • Level shifters and isolators - needed to try advanced power saving strategies in digital logic
The current initial design of the digital segment of our chip is best shown in a block diagram below:




We will talk of flows and the analogue integration later.....

Thursday, 3 September 2009

The sheer size of an old Sun "midrange" server

This one is going back a bit but I have obtained it for legacy support. Its a Sun V880 with 6x UltraSPARC III 750MHz processors and 12GB of RAM. Still a computer to be reckoned with [Update: Spent $50 on a new CPU/RAM board to take it to 8x CPU and 16GB RAM. eBay is great for this kind of thing]



Its as high as my desk, as large as a fridge lying on its side and sounds like a very loud aircon. [Update: When it is running under an OS at low load it throttles the fans and becomes quite quiet]

This one was going to be built with Solaris 10 on a software mirrored root using UFS but the new spin of Solaris 10 allows installation and booting off ZFS. A much more sensible choice when I have 6x 36GB disks.

Thursday, 20 August 2009

Modding an HP Proliant DL585 to take an EVE Zebu UF2

I am the proud "controller" of an EVE Zebu UF2 emulation accelerator (a big PCI card covered in FPGAs). One of its biggest selling points is their Transactors which allow you to present your design with the interfaces it would experience if it were real, completely abstracting away the PCI bus.

However when I say big I mean triple height and full length. It uses 64 bit PCI/66. (For those considering purchasing a UF4 card most PCs can't fit it as it is larger still).

So I need a computer to host it in!

Enter the HP DL585 - a lovely machine. Built as solidly as a tank and everything is terribly easily accessible either from the front or the top. Everything. At a push I think I could swap out the motherboard and be back up and running in 30 minutes from cracking the case.

The original engineers designed it for cable-less operation (and very nearly succeeded!) but the EVE ZeBu-UF needs power from a 4 pin molex (found on most pre-SATA HDDs).

So what to do? Spotting this SCA backplane and knowing that HDDs take 12V, 5V and 3.3V power I had my solution. Mod a molex connector onto the pins on the back of one of the SCA sockets.

Firstly I checked the specifications for the ZeBu: 25W at 12V which is a current of 2.08A. Secondly I checked the specifications of the SCA2 connector: Section 6.4.1 of the SFF-8046 standard specifies a surge current of 5A and a constant supply of 2.5A. This means that one socket can supply the necessary power.

However, several provisos first: This will void your warranty. The SCA-2 connector transfers power to the drive using several pins for each voltage (12V, 5V and 3.3V) to reduce their resistivity to high current. By design the clusters of pins supplying the same voltage are next to each other making it easier. Probe for the resistance between the pins you think are the right ones - it needs to be zero.

The mod requires soldering the little clusters of pins together with fine wire (get some strands out of a multistrand wire) and then attached the cables. Note - don't include the Precharge pins - wiring them to the rest of the supply could cause unexpected operation as they will no longer function correctly when you insert a HDD in the front. After you are done, check, double check and triple check. Use a magnifier/microscope to check the soldering. Clean the area of any bits of solder. Probe the resistivity again. This could be an expensive mistake if there is a problem!

Power on (fingers crossed) and bingo - 12V and 5V.

Here is a photo of the modded card in position:


...and a photo of the UF2 in the PCI bay (I have two power connectors just in case I can get another UF2 - wishful thinking I know):

Thursday, 23 July 2009

Loading new maps into Nokia Maps on an N95 without a cable or bluetooth

Foolishly I arrived in San Francisco for MSE without loading the California maps into my phone.

This presented me with a pretty conundrum. Nokia's recent upgrade to Ovi Maps meant that the new maps uploader wanted a phone connected with Nokia PC Suite via the USB-A to Mini-B cable or bluetooth in PCSuite mode.

However without a cable or bluetooth (I have my old IBM X31 laptop, hand upgraded with Intel 2200BG Wifi) what can you do?

Turn to an almost forgotten technology: IrDa. The N95 8GB has a 115200 IrDa port on it and the Thinkpad X31 has a 4Mbps one.
  1. Download the old "Nokia Map Loader" - this talks to the phone as a mass storage device.
  2. Connect the phone via IrDa to the PCSuite.
  3. Run the Nokia Map Loader
Upload the maps - took a very long time!

[An alternative to doing this is use the following blog post to download the maps directly. This can even be done on your mobile!]

Friday, 17 July 2009

Off to Microelectronic Systems Education

...in sunny San Francisco.

MSE Conference (and its partner EWME) provide a fantastic venue to explore and demonstrate novel ways to teach complex system-on-chip designs.

I shall also be attending the tutorials - One on the Cypress PSoC platform, a fascinating combination of a digital microcontroller, a programmable logic device and a section of programmable analogue logic. The second will be on several techniques from Synopsys:

  1. Structured Methodology for Successful Low Power Verification
  2. Power-Performance Optimization of Digital Circuits

Sunday, 12 July 2009

Fix for amanda 2.5.1p1 on MacOSX PowerPC

Bug causes the following error message in the following stable releases 2.5.1p1, 2.5.1p3, 2.6.1p1

Amanda Backup Client Hosts Check
--------------------------------
ERROR: NAK mac-mini: user backup from hs-dhgl7ce.msindustries.com is not
allowed to execute the service noop: /Users/amandabackup/.amandahosts:
owned by id 5000, should be 529288
Client check: 1 host checked in 0.859 seconds, 1 problem found

There is no user of UID of 529288 on the machine.

Here is a snip of the amandad log after a modification to add Print statements printing the UID as dereferenced from the pointer in check_user_amandahosts() in common-src/security-util.c


amandad: time 0.187: sec: calling accept_fn
Print uid: 5000
Print UID on entry now: 5000
check_user_amandahosts(host=hs-dhgl7ce.msindustries.com, pwd=0x100400, remoteuse
r=backup, service=selfcheck)
amandad: bsd: processing file: /Users/amandabackup/.amandahosts
amandad: bsd: owner=amandabackup group=wheel mode=600
Print UID after stralloc: 529288
Print UID after fopen: 529288
Print sbuf.st_uid now: 5000
Print UID after fstat: 529288
amandad: bsd: processing line: hs-dhgl7ce.msindustries.com backup="" amdump=""
amandad: bsd: comparing "hs-dhgl7ce.msindustries.com" with


The bug has been fixed by caching the pwd->ps_uid at the start of the function and using the test against that. Also note that the bug behavior changed at some point as the UID changed from 529288 to 0. Suggests a buffer overrun, endianness or thread issues.

Here is the modified check_user_amandahosts() security-util.c (don't forget to modify the top of the file to enable secprintf().


/*
* Check to see if a user is allowed in. This version uses .amandahosts
* Returns -1 on failure, or 0 on success.
*/
char *
check_user_amandahosts(
const char * host,
struct in_addr addr,
struct passwd * pwd,
const char * remoteuser,
const char * service)
{
char *line = NULL;
char *filehost;
const char *fileuser;
char *ptmp = NULL;
char *result = NULL;
FILE *fp = NULL;
int found;
struct stat sbuf;
char n1[NUM_STR_SIZE];
char n2[NUM_STR_SIZE];
int hostmatch;
int usermatch;
char *aservice = NULL;

uid_t tmp_pw_uid = pwd->pw_uid;
secprintf(("Print UID on entry now: %d\n",pwd->pw_uid));

secprintf(("check_user_amandahosts(host=%s, pwd=%p, "
"remoteuser=%s, service=%s)\n",
host, pwd, remoteuser, service));

ptmp = stralloc2(pwd->pw_dir, "/.amandahosts");
#if defined(SHOW_SECURITY_DETAIL) /* { */
show_stat_info(ptmp, "");;
#endif /* } */
secprintf(("Print UID after stralloc: %d\n",pwd->pw_uid));
if ((fp = fopen(ptmp, "r")) == NULL) {
result = vstralloc("cannot open ", ptmp, ": ", strerror(errno), NULL);
amfree(ptmp);
return result;
}
secprintf(("Print UID after fopen: %d\n",pwd->pw_uid));

/*
* Make sure the file is owned by the Amanda user and does not
* have any group/other access allowed.
*/
if (fstat(fileno(fp), &sbuf) != 0) {
result = vstralloc("cannot fstat ", ptmp, ": ", strerror(errno), NULL);
goto common_exit;
}
secprintf(("Print sbuf.st_uid now: %d\n",sbuf.st_uid));
secprintf(("Print UID after fstat: %d\n",pwd->pw_uid));

/*if (sbuf.st_uid != pwd->pw_uid) {*/
if (sbuf.st_uid != tmp_pw_uid) {
snprintf(n1, SIZEOF(n1), "%ld", (long)sbuf.st_uid);
snprintf(n2, SIZEOF(n2), "%ld", (long)pwd->pw_uid);
result = vstralloc(ptmp, ": ",
"owned by id ", n1,
", should be ", n2,
NULL);
goto common_exit;
}