Wednesday, 13 August 2008

STmicroelectronic 65nm, 65nm SOI and 45nm Design Kit NDA's Signed

Never underestimate the time it takes to sign a legal commitment! Finally I found the right person who was able to sign for the University binding us to not revealing secrets and accepting liabilities such that I can now receive the STMicroelectronic Design Kits (Cadence calls them PDK's) from CMP for their 65nm, 65nm SOI and 45nm CMOS processes.

Now to develop several flows including various verification strategies and frontends (Synopsys' Designware, Cadence IC, PrimeTime, etc).

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