- Day 1: Intro, design environment and toolchain + LAB
- Day 2: Leakage aware design and prevention, floorplanning LAB, design planning and libraries (including IP, soft and hard).
- Day 3: Low power flow including positioning to minimise dynamic and leakage power, physical synthesis placement and optimisation. Multiple Clock Tree Synthesis.
- Day 4: Physical Synthesis, Design for Test, Multimode and Multicorner, Routing to GDSII and labs.
- Day 5: IR drop analysys, dynamic power analysis, on chip validation and statistical static timing analysis. Lab on signoff, signoff and design finishing and layout verification. Tape-out.
Monday, 28 July 2008
I get to attend the IDESA "Advanced Digital Physical Implementation flow" Course
IDESA is intended to kickstart the production of both analog and digital <=90nm CMOS among academia. I have got a place on the Advanced Digital Physical Implementation flow course hosted by Rutherford Appleton Laboratories in Didcot, Oxfordshire (the courses are available from other host institutions as well). The week looks very interesting: